參數資料
| 型號： | PI7C9X7954AFDE |
| 廠商： | Pericom |
| 文件頁數： | 21/70頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE-TO-UART BRIDGE 128LQFP |
| 標準包裝： | 90 |
| 應用： | PCIe至UART橋接 |
| 接口： | 高級配置電源接口（ACPI） |
| 電源電壓： | 1.8V, 3.3V |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應商設備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X7954
PCI Express Quad UART
Datasheet
Page 28 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Programming
Interface
RO
Read as 02h to indicate no programming interfaces have been
defined for PCI-to-PCI bridges
23:16
Sub-Class Code
RO
Read as 00h to indicate device is PCI-to-PCI bridge
31:24
Base Class Code
RO
Read as 07h to indicate device is a bridge device
6.2.7.
CACHE LINE REGISTER – OFFSET 0Ch
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Cache Line Size
RW
The cache line size register is set by the system firmware and the
operating system to system cache line size. This field is implemented
by PCI Express devices as a RW field for legacy compatibility
purposes but has no impact on any PCI Express device functionality.
Reset to 00h.
6.2.8.
MASTER LATENCY TIMER REGISTER – OFFSET 0Ch
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Latency timer
RO
Does not apply to PCI Express. Must be hardwired to 00h.
6.2.9.
HEADER TYPE REGISTER – OFFSET 0Ch
BIT
FUNCTION
TYPE
DESCRIPTION
23:16
Header Type
RO
Read as 00h to indicate that the register layout conforms to the
standard PCI-to-PCI bridge layout.
6.2.10. BASE ADDRESS REGISTER 0 – OFFSET 10h
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Base Address 0
RW
Use this I/O base address to map the UART 16550 compatible
registers.
The base address can be allocated to 64 Bytes.
Reset to 00000001h.
6.2.11. BASE ADDRESS REGISTER 1 – OFFSET 14h
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Base Address 1
RW
Use this memory base address to map the UART 16550 compatible
and enhanced registers.
The base address can be allocated to 4096 Bytes.
Reset to 00000000h
6.2.12. SUBSYSTEM VENDOR REGISTER – OFFSET 2Ch
BIT
FUNCTION
TYPE
DESCRIPTION
15:0
Sub Vendor ID
RO
Indicates the sub-system vendor id. The default value may be
changed by auto-loading from EEPROM.
Reset to 0000h.
6.2.13. SUBSYSTEM ID REGISTER – OFFSET 2Ch
BIT
FUNCTION
TYPE
DESCRIPTION
31:16
Sub System ID
RO
Indicates the sub-system device id. The default value may be
changed by auto-loading from EEPROM.
Reset to 0000h.
13-0093
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