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PI7C9X7954
PCI Express Quad UART
Datasheet
Page 44 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
7. UART REGISTER DESCRIPTION
7.1. REGISTERS IN I/O MODE
Each UART channel has a dedicated 8-byte register block in I/O mode. The register block can be accessed
the UART I/O Base Address, which is obtained by adding the UART Register Offset to the content of the
Base Address Register 0 (BAR0). The following diagram shows the arrangement of individual UART
register blocks.
000h
UART0 Registers
008h
UART1 Registers
010h
UART2 Registers
UART3 Registers
038h
UART I/O Base Address
(BAR0 + UART Register Offset)
UART Register Offset
Figure 7-1 UART Register Block Arrangement in I/O Mode
Table 7-1 UART Base Address in I/O Mode
UART
UART I/O Base Address
UART0
BAR0 + 000h
UART1
BAR0 + 008h
UART2
BAR0 + 010h
UART3
BAR0 + 038h
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