Pericom Semiconductor 31 – 24 23 – 16 15 – 8 7 – 0 BYTE OFFSET" />
參數(shù)資料
型號： PI7C9X7954AFDE
廠商： Pericom
文件頁數(shù)： 19/70頁
文件大?。?/td> 0K
描述： IC PCIE-TO-UART BRIDGE 128LQFP
標(biāo)準(zhǔn)包裝： 90
應(yīng)用： PCIe至UART橋接
接口： 高級配置電源接口（ACPI）
電源電壓： 1.8V, 3.3V
封裝/外殼： 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X7954
PCI Express Quad UART
Datasheet
Page 26 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
31 – 24
23 – 16
15 – 8
7 – 0
BYTE OFFSET
Reserved
F4h - FCh
Other than the PCI 2.3 compatible configuration space header, the I/O bridge also implements
PCI express extended configuration space header, which includes advanced error reporting
registers. The following table details the allocation of the register fields of PCI express
extended capability space header. The first extended capability always begins at offset 100h
with a PCI Express Enhanced Capability header and the rest of capabilities are located at an
offset greater than 0FFh relative to the beginning of PCI compatible configuration space.
31 – 24
23 – 16
15 – 8
7 – 0
BYTE OFFSET
Next Capability
Offset = 000h
Capability Version
PCI Express Extended Capability
ID = 001h
100h
Uncorrectable Error Status Register
104h
Uncorrectable Error Mask Register
108h
Uncorrectable Error Severity Register
10Ch
Correctable Error Status Register
110h
Correctable Error Mask Register
114h
Advanced Error Capabilities and Control Register
118h
Header Log Register
11Ch~128h
6.2.1.
VENDOR ID REGISTER – OFFSET 00h
BIT
FUNCTION
TYPE
DESCRIPTION
15:0
Vendor ID
RO
Identifies Pericom as the vendor of this I/O bridge. The default
value may be changed by auto-loading from EEPROM.
Reset to 12D8h.
6.2.2.
DEVICE ID REGISTER – OFFSET 00h
BIT
FUNCTION
TYPE
DESCRIPTION
31:16
Device ID
RO
Identifies this I/O bridge as the PI7C9X7954. The default value may
be changed by auto-loading from EEPROM.
Reset to 7954h.
6.2.3.
COMMAND REGISTER – OFFSET 04h
BIT
FUNCTION
TYPE
DESCRIPTION
0
I/O Space Enable
RW
Controls a device’s response to I/O Space accesses. A value of 0
disables the device response. A value of 1 allows the device to
respond to I/O Space accesses.
Reset to 0b.
1
Memory Space
Enable
RW
Controls a device’s response to Memory Space accesses. A value of 0
disables the device response. A value of 1 allows the device to
response to memory Space accesses.
Reset to 0b.
2
Bus Master Enable
RO
It is not implemented. Hardwired to 0b.
3
Special Cycle
Enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
4
Memory Write And
Invalidate Enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
5
VGA Palette Snoop
Enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
6
Parity Error
Response Enable
RW
Controls the device’s response to parity errors. When the bit is set,
the device must take its normal action when a parity error is
detected. When the bit is 0, the device sets its Detected Parity Error
Status bit when an error is detected.
13-0093
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