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參數(shù)資料
| 型號： | PI7C9X7954AFDE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 31/70頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE-TO-UART BRIDGE 128LQFP |
| 標準包裝： | 90 |
| 應用： | PCIe至UART橋接 |
| 接口： | 高級配置電源接口（ACPI） |
| 電源電壓： | 1.8V, 3.3V |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應商設備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X7954
PCI Express Quad UART
Datasheet
Page 37 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
3
Unsupported
Request Reporting
Enable
RW
0b: Disable Unsupported Request Reporting.
1b: Enable Unsupported Request Reporting.
Reset to 0b.
4
Enable Relaxed
Ordering
RO
It is not implemented.
Reset to 0b.
7:5
Max_Payload_Size
RW
This field sets maximum TLP payload size for the device.
Permissible values that can be programmed are indicated by the
Max_Payload_Size Supported in the Device Capabilities register.
Any value exceeding the Max_Payload_Size Supported written to
this register results into clamping to the Max_Payload_Size
Supported value.
Reset to 000b.
8
Extended Tag Field
Enable
RO
It is not implemented. Hardwired to 0b.
9
Phantom Function
Enable
RO
It is not implemented. Hardwired to 0b.
10
Auxiliary (AUX)
Power PM Enable
RWS
When set, indicates that the I/O bridge is enabled to draw AUX
power independent of PME AUX power.
Reset to 0b.
11
Enable No Snoop
RO
It is not implemented. Hardwired to 0b.
14:12
Max_Read_
Request_Size
RO
It is not implemented. Hardwired to 000b.
15
Reserved
RO
Reset to 0b.
6.2.52. DEVICE STATUS REGISTER – OFFSET E8h
BIT
FUNCTION
TYPE
DESCRIPTION
16
Correctable Error
Detected
RW1C
Asserted when correctable error is detected. Errors are logged in this
register regardless of whether error reporting is enabled or not in the
Device Control register.
Reset to 0b.
17
Non-Fatal Error
Detected
RW1C
Asserted when non-fatal error is detected. Errors are logged in this
register regardless of whether error reporting is enabled or not in the
Device Control register.
Reset to 0b.
18
Fatal Error Detected
RW1C
Asserted when fatal error is detected. Errors are logged in this
register regardless of whether error reporting is enabled or not in the
Device Control register.
Reset to 0b.
19
Unsupported
Request Detected
RW1C
Asserted when unsupported request is detected. Errors are logged in
this register regardless of whether error reporting is enabled or not in
the Device Control register.
Reset to 0b.
20
AUX Power
Detected
RO
Asserted when the AUX power is detected by the I/O bridge
Reset to 1b.
21
Transactions
Pending
RO
It is not implemented. Hardwired to 0b.
31:22
Reserved
RO
Reset to 000h.
6.2.53. LINK CAPABILITIES REGISTER – OFFSET ECh
BIT
FUNCTION
TYPE
DESCRIPTION
13-0093
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