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PI7C9X7954
PCI Express Quad UART
Datasheet
Page 34 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
6.2.40. Power Management Control Parameter – OFFSET B8h
BIT
FUNCTION
TYPE
DESCRIPTION
5:0
Power Management
Control Parameter
RW
The default value may be changed by auto-loading from EEPROM.
Reset to 000001b.
31:6
Reserved
RO
Reset to 0000000h.
6.2.41. DEBUG REGISTER 1 – OFFSET BCh (Test Purpose Only)
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Debug Register 1
RO
Used for test purpose only.
Reset to 00000000h.
6.2.42. DEBUG REGISTER 2 – OFFSET C0h (Test Purpose Only)
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Debug Register 2
RO
Used for test purpose only.
Reset to 00000000h.
6.2.43. DEBUG REGISTER 3 – OFFSET C4h (Test Purpose Only)
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Debug Register 3
RO
Used for test purpose only.
Reset to 00000000h.
6.2.44. DEBUG REGISTER 4 – OFFSET C8h (Test Purpose Only)
BIT
FUNCTION
TYPE
DESCRIPTION
0
Low Driver Current
HwInt
It indicates the status of the strapping pin LODRV. The default value
may be changed by auto-loading from EEPROM.
1
High Driver Current
HwInt
It indicates the status of the strapping pin HIDRV. The default value
may be changed by auto-loading from EEPROM.
5:2
Driver Transmit
Current
HwInt
It indicates the status of the strapping pins DTX[3:0]. The default
value may be changed by auto-loading from EEPROM.
9:6
De-emphasis
Transmit
Equalization
HwInt
It indicates the status of the strapping pins DEQ[3:0]. The default
value may be changed by auto-loading from EEPROM.
11:10
Receive
Termination
Adjustment
HwInt
It indicates the status of the strapping pins RXTRMADJ[1:0]. The
default value may be changed by auto-loading from EEPROM.
13:12
Transmit
Termination
Adjustment
HwInt
It indicates the status of the strapping pins TXTRMADJ[1:0]. The
default value may be changed by auto-loading from EEPROM.
31:14
Reserved
RO
Reset to 00000h.
6.2.45. GPIO CONTROL REGISTER – OFFSET D8h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
GPIO Input
RO
The current state of the GPIO[x] pin can be read from bit[x] in this
register, where x=7 to 0. The bits are effective only when the
corresponding GPIO I/O Enable bits are set to “0”.
13-0093