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| 型號(hào)： | OR3TP12 |
| 英文描述： | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| 中文描述： | 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口 |
| 文件頁(yè)數(shù)： | 86/128頁(yè) |
| 文件大小： | 2450K |
| 代理商： | OR3TP12 |
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ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
86
L Lucent Technologies Inc.
PCI Bus Core Target Controller Detailed
Description
(continued)
FPSC Configuration
The OR3TP12 FPSC provides the designer many
FPGA configuration options. In addition to all the con-
figuration options provided in the standard Series 3
architecture (except Master parallel mode) the
OR3TP12 PCI FPSC can also be configured via the
PCI interface. This feature is possible since the PCI
interface is functional even before the FPSC has been
configured. With this capability, many configuration
schemes can be implemented. For example, a generic
FPSC configuration can be loaded via a serial configu-
ration PROM and updated via the PCI bus or the micro-
processor interface. The FPSC can also be
reprogrammed in the field, or the configuration can be
dynamically modified to perform different tasks.
In a proprietary system or using one FPSC, the system
software can locate the OR3TP12 by reading the ven-
dor ID and device ID. Once identified, any PCI agent
can write 32-bit words into the PCI Configuration regis-
ter at address 0x44. This data is then serially shifted
into the FPGA configuration logic, and distributed to the
FPSC programmable resources as if the data was from
an external serial PROM.
When multiple FPSCs are configured via the PCI inter-
face in a standard PCI system, there can be an identifi-
cation issue that must be resolved. The subsystem
vendor ID and subsystem ID that reside at 2Ch—2Fh in
the PCI configuration space contains default values
after power-up, but before configuration. These identifi-
cation values are usually needed by system software to
identify where an OR3TP12 resides on the PCI bus,
and which FPSC configuration bit stream to use for
each OR3TP12. Therefore, for multiple FPSCs being
configured employing the PCI interface, each should be
initialized via a small serial PROM after power-up. This
initialization bit stream will contain a unique subsystem
and/or subsystem vendor ID (defined by the FPSC con-
figuration manager) to describe each device operation
in the system. For the FPGA design in the initialization
bit stream, all embedded core input controls signals
should be tied to their inactive state, especially
t_retryn
and
t_abort
to allow access to the PCI config-
uration space. To minimize the size of this initial bit
stream, use the options available in bit stream genera-
tion process to use explicit addressing, and remove
zero data frames.
This initial configuration bit stream is only required to
provide correct subsystem vendor ID and subsystem
ID values for system software use, but it may, in addi-
tion, be the first version of the FPSC’s application code.
The PCI system software is then able to invoke the
proper procedures that will reconfigure the OR3TP12
using the final version of the application.
FPGA Configuration via PCI Bus
The OR3TP12 is configured using registers located at
0x40 hex and 0x44 hex in the PCI configuration space.
These registers are dedicated to the OR3TP12 config-
uration and readback functions and are detailed in
Table 25. The FPGA configuration control-status regis-
ter (FCCSR) is a 16-bit register at address 0x40 hex,
and the FPGA configuration data register (FCDR) is a
32-bit register at address 0x44 hex.
The following is an example sequence which config-
ures the OR3TP12 via the PCI interface:
1. Read the vendor ID (0x0) and device ID (0x0) regis-
ters. If the vendor ID is 0x11C1 hex, the vendor is
Lucent. If the device ID is 0x5400 hex, the device is a
Lucent OR3TP12 PCI FPSC
2. If using an auxiliary initialization device (serial
PROM, MPI, etc.) for subsystem ID identification
setup, read the FCCSR (0x40) until DONE (bit 1)
goes active-high. This indicates that the bit stream
for subsystem ID initialization has loaded.
3. Read the class code, revision ID, subsystem vendor
ID, and subsystem ID registers. This information has
been programmed into the FPSC by an initialization
bit stream or is the powerup default. It can be used
by the configuration software to locate the correct
OR3TP12 configuration bit stream and driver for the
OR3TP12s application.
4. Read the FCCSR (0x40) until ASBMODE (bit 0)
goes active-high, indicating that the JTAG controller
is not in control of the FPGA configuration logic.
5. Toggle PRGRMN (bit 12) in the FCSSR (0x40) low to
reset the current the FPGA configuration. Write to
the FCCSR (0x40) three times, first with PRGMN
high, then active-low, then high.
6. Write to the FCCSR (0x40) with ConfigFPGA (bit 14)
active-high. This will initiate an FPGA configuration
session via the PCI interface.
7. Read the FCCSR (0x40) until SREMPTY (bit 4) goes
active-high, indicating that the configuration shift reg-
ister is ready for data.
8. Write a 32-bit word of OR3TP12 configuration data
to the FCDR (0x44), noting that bit 32 will be the first
bit to exit the shift register to the FPGA configuration
logic.
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