參數(shù)資料
型號： OR3TP12
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）嵌入式主/目標PCI接口
文件頁數(shù)： 61/128頁
文件大小： 2450K
代理商： OR3TP12
Lucent Technologies Inc.
Lucent Technologies Inc.
61
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Target Controller Detailed Description
(continued)
5-7362(F)
Figure 19. Target Write Single (FIFO Interface, Quad-Port)
Example: Target Write Memory Burst Transaction
Figure 20 shows the timing on the PCI bus for a Target memory write burst of four 32-bit words. The timing on the
PCI interface is typical for a medium-speed decode Target. Note that
trdyn
is asserted at the earliest possible time,
which is concurrent with assertion of
devseln
. In the example of a 4-word burst, the Target write FIFO is not filled,
so execution continues to completion. This would also be the case for a burst of any length when the FPGA appli-
cation is capable of unloading the FIFO as fast as the PCI interface is loading it. If the Target write FIFO becomes
full, the Target can disconnect without data on the first data word it cannot accept (
twburstpendn
= 1), or insert up
to eight wait-states (
twburstpendn
= 0).
The timing on the dual-port FIFO interface (Figure 21) shows the first indication to the FPGA application that a new
operation has begun by the assertion of Target request (
treqn
). When
treqn
is valid, the FPGA application begins
the command/address phase by asserting Target address enable (
taenn
) and accepting the command from bus
tcmd
and address from bus
datatofpga
(
x
) (with
fifo_sel
= 1). A burst operation and dual-address indication
accompanies the address on
datatofpgax[1]
and
datatofpgax[0]
respectively. The FPGA application continues to
receives new address data (
taenn
asserted) on every clock until
twlastcycn
is asserted, indicating the end of the
command/address phase. See command/address section for notes regarding address transfer and alignment.
1
T0
T1
T2
T3
T4
T5
0
1
4
5
0
CMD
ADRS0
ADRS1
D0
D1
fclk
tstatecntr
t_ready
treqn
tcmd
twdata
taenn
tw_emptyn
twdataenn
twlastcycn
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