參數(shù)資料
型號(hào)： OR3TP12
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口
文件頁(yè)數(shù)： 18/128頁(yè)
文件大?。?/td> 2450K
代理商： OR3TP12
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ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
18
L Lucent Technologies Inc.
PCI Bus Core Detailed Description
(continued)
PCI Bus Pin Information
This section describes signals on the PCI bus interface and at the embedded core/FPGA interface. Some signal
definitions change name and location based on the mode of operation. Modes of operation are described following
the signal descriptions. PCI bus signal package pin locations can be found in Table 42 through .
Table 5. PCI Bus Pin Descriptions
Symbol
I/O
Description
System Pins
clk
I
Clock.
Provides timing for all transactions on the PCI bus and is an input to the
OR3TP12 device. All PCI signals, except
rstn
and
intan
, are sampled on the rising
edge of
clk
, and all other PCI bus timing parameters are defined with respect to this
edge.
clk
operates up to 66 MHz, and the minimum frequency is dc.
Reset.
An active-low signal used to reset the entire PCI bus.
rstn
is asynchronous
to
clk
. When asserted, all PCI output signals are 3-stated.
rstn
I
Address and Data Pins
ad[31:0]
I/O
Address and Data.
Multiplexed on the same PCI pins. A PCI bus transaction con-
sists of an address phase followed by one or more data phases.
During data phases,
ad[7:0]
contain the least significant byte and
ad[31:24]
con-
tain the most significant byte. During memory commands, the
ad[31:2]
lines spec-
ify the address and
ad[1:0]
specify the type of bursting sequence to use. The table
below outlines the bursting sequence based on the values of
ad[1:0]
for the Target.
ad[1:0]
Bursting sequence.
00
Linear incrementing accepted by the Target.
01
Target disconnect after first transfer.
10
Target disconnect after first transfer.
11
Target disconnect after first transfer.
Bus Command and Byte Enables.
Active-low signals multiplexed on the same
PCI pins. During the address phase of a transaction,
c_ben[3:0]
define the bus
command. During the data phase,
c_ben[3:0]
are used as byte enables. The byte
enables are valid for the entire data phase and determine which byte lanes carry
meaningful data.
Parity.
Specifies even parity across
ad[31:0]
and
c_ben[3:0]
.
par
is stable and
valid one clock after the address phase. For data phases,
par
is stable and valid
one clock after
irdyn
is asserted on a write transaction or
trdyn
is asserted on a
read transaction. Once
par
is valid, it remains valid until one clock after the comple-
tion of the current data phase. The Master drives
par
for address and write data
phases; the Target drives
par
for read data phases.
c_ben[3:0]
I/O
par
I/O
Interface Control Pins
framen
I/O
Cycle Frame.
An active-low signal driven by the current Master to indicate the
beginning and duration of an access.
framen
is asserted to indicate a bus transac-
tion is beginning. While
framen
is asserted, data transfers continue. When
framen
is deasserted, the transaction is in the final phase or has completed.
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