參數(shù)資料
型號： OR3TP12
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）嵌入式主/目標PCI接口
文件頁數(shù)： 22/128頁
文件大?。?/td> 2450K
代理商： OR3TP12
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
22
L Lucent Technologies Inc.
Symbol
I/O
Description
Clock
Domain
Master Write Data FIFO Signals
mwlastcycn
O
Master Write Last Data Cycle.
This active-low signal has two functions:
a.
It is asserted low to indicate that the current Master start address word is the
final portion being sent. It can be asserted prior to any address portion being
transferred, indicating to use the previous stored address in the selected
Master holding register.
maenn
must be asserted with
mwlastcycn
during
the final address word.
b.
It is asserted low to indicate that the accompanying Master write data is the
final data for this operation.
mwdataenn
must be asserted with
mwlastcycn
during the final data word.
Master Write FIFO Data Enable.
This active-low signal enables the registering
of data bus
mwdata
(quad-port mode) or
datafmfpga
(dual-port mode) during
Master write operations into the Master write data FIFOs.
mwdataenn
should
not be asserted when the Master write data FIFOs are full, or data may be lost.
Master Write PCI Bus Hold.
For Master write transfers on the PCI bus, this
signal delays the start of the transfer (i.e.,
reqn
asserted) on the PCI bus,
allowing the FPGA application to fill the Master write data FIFO. The transac-
tion will begin when
mwpcihold
is deasserted or the Master write data FIFO
becomes full.
mwpcihold
should be deasserted before
mwlastcycn
is
asserted, and
needs to remain asserted for a minimum of two
pciclk
cycles.
Master Write Data FIFO Almost Full Flag.
This active-low signal indicates
that only four more empty 64-bit locations remain in the Master write data
FIFO.
Master Write Data FIFO Full Flag.
This active-low signal indicates that the
Master write data FIFO is full.
mwdataenn
should never be asserted when
mw_fulln
is active.
fclk
*
mwdataenn
O
fclk
*
mwpcihold
O
pciclk
mw_afulln
I
fclk
*
mw_fulln
I
fclk
*
* The source of the clock (
fclk1
or
fclk2
) for the FIFO interface (Master or Target) is selected in the FPSC configuration manager.
PCI Bus Core Detailed Description
(continued)
Table 6. Embedded Core/FPGA Interface Signals
(continued)
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