參數(shù)資料
型號： OR3TP12
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）嵌入式主/目標(biāo)PCI接口
文件頁數(shù)： 31/128頁
文件大小： 2450K
代理商： OR3TP12
Lucent Technologies Inc.
Lucent Technologies Inc.
31
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description
(continued)
Embedded Core Configuration Options
Table 8 lists all options in the embedded core that can be selected via the FPSC configuration manager. The table
also lists the settings available for each option, which is accessible using the FPSC design kit software.
Table 8. PCI Bus Core Options Settable via FPGA Configuration RAM Bits
Description
Hex Address in PCI
Configuration
Space
0x08
0x09—0x0B
0x4: Bit 2
Optional Settings
Revision ID
Class Code
Bus Master Support
Any 8-bit value.
Any 24-bit value.
Three options:
I
Target Only: Powerup value: 0; Access Type:
Read-only
I
Master/Target: Powerup value: 0; Access Type:
Read/Write
I
Master: Powerup value: 1; Access Type: Read-
only
Mask value for wire-OR output
pci_cfg_stat
.
Mask value for wire-OR output
pci_cfg_stat.
Mask value for wire-OR output
pci_cfg_stat.
Mask value for wire-OR output
pci_cfg_stat
.
Mask value for wire-OR output
pci_cfg_stat
.
Mask value for wire-OR output
pci_cfg_stat
.
Any 8-bit value divisible by eight (XXXXX000).
I
Refer to PCI Specification 2.2, Section 6.2.5.1
I
Up to two 32-bit BARs, one 64-bit BAR, or none
(i.e., unprogrammed).
I
32-bit BARs can Target memory or I/O space.
I
Memory can be prefetchable or nonprefetchable.
I
If 64-bit BAR, must be memory; page size can be
from 2
4
bytes to 2
64
bytes.
I
If 32-bit I/O BAR, page size can be from 2
2
bytes
to 2
32
bytes.
I
If 32-bit memory BAR, address space can be 2
4
bytes
to the maximum (2
20
bytes or 2
32
bytes).
Same as for BAR area 1.
Data Parity Error Detected
Target Abort Signal
Target Abort Received
Master Abort Received
System Error Signaled
Parity Error Detected
Latency Timer Initial Value
Base Address Register (BAR0/1)
Area 1
0x4: Bit 8
0x4: Bit 11
0x4: Bit 12
0x4: Bit 13
0x4: Bit 14
0x4: Bit 15
0x0D
0x10—0x17
Base Address Register (BAR2/3)
Area 2
Base Address Register (BAR4/5)
Area 3
0x18—0x1F
0x20—0x27
Same as for BAR area 1.
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