參數(shù)資料
型號(hào)： OR3TP12
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口
文件頁數(shù)： 84/128頁
文件大?。?/td> 2450K
代理商： OR3TP12
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
84
L Lucent Technologies Inc.
PCI Bus Core Target Controller Detailed Description
(continued)
Table 25. Configuration Space Assignment
(continued)
1. These values are intended to be custom assigned, per the intended application, by assigning constants via the FPGA configuration manager.
2. These bits exhibit special behavior per the PCI Specification:
— Reads behave normally.
— Writing a one clears the bit to 0.
— Writing a 0 has no effect on the bit.
3. Bytes 10—27 hex contain the base address registers (BARs).
— Any legal combination of memory and I/O BARs is permitted, as long as 64-bit BARs are naturally aligned, that is, they occupy bytes
10—17, 18—1F, or 20—27 hex.
— Memory BARs may be marked as prefetchable/nonprefetchable by setting/resetting bit 3; however, the PCI bus core’s behavior is not
affected by this setting. In particular, the Target read operation may discard unused FIFO read-ahead data even though the data space is
marked as nonprefetchable (this is not a violation since the nonprefetchable bit only says that data can’t be discarded once it has been
sent over the PCI bus; nevertheless, caution must be exercised when this bit is reset).
4. These signals are tied to the FPGA signal of the same name and are not initialized.
5. These bits exhibit special behavior per the CompactPCI Hot Swap Specification:
— Reads behave normally.
— Writing a one clears the bit to 0.
— Writing a 0 has no effect on the bit.
6. This 32-bit register is used during manufacturing test. Writes are not allowed; reads are allowed and cause no side effects, but the value
returned is undefined.
Bytes
Width
Bit
Description
Read/Write
Initial Value after
FPGA
Configuration
Note 1
Note 1
zeros
08
8
—
—
—
Revision ID
Class Code
Cache Line Size
Latency Timer:
Programmable Portion
Granularity eight clks
Header Type
BIST
Base Address Register
Cardbus CIS Pointer
Subsystem Vendor ID
Subsystem ID
Expansion ROM Base Address
Capabilities Pointer
(Reserved)
(Reserved)
Interrupt Line
Interrupt Pin
Min_Gnt
Max_Lat
Read Only
Read Only
Read Only
09—0B
0C
0D
24
8
8
7—3
2—0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Read/Write
Read Only
Read Only
Read Only
Note 3
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read/Write
Read Only
Read Only
Read Only
Near 1
zeros
00h
zeros
Note 1
zeros
zeros
Note 1
zeros
50h
zeros
zeros
zeros
01h (
intan
)
Note 1
Note 1
0E
0F
8
8
10—27
28—2B
2C—2D
2E—2F
30—33
34
35—37
38—3B
3C
3D
3E
3F
192
32
16
16
32
8
24
32
9
8
8
8
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