參數(shù)資料
型號(hào)： OR3TP12
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口
文件頁(yè)數(shù)： 66/128頁(yè)
文件大?。?/td> 2450K
代理商： OR3TP12
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ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
66
L Lucent Technologies Inc.
PCI Bus Core Target Controller Detailed
Description
(continued)
Although, the signal
deltrn
is used
to enter into
delayed mode, all Target read transactions automati-
cally enter delayed mode on a retry. For example, if the
Target inserted 16/32 wait-states on the initial read
access and no data was provided to the Target read
data FIFO causing a disconnect, the transaction will
revert into delayed mode. On the following external
Master accesses, if no data was available in the Target
read data FIFO, an immediate retry would be issued
with no wait-states.
I/O Reads
I/O reads differ only from memory reads in that I/O
reads always perform a disconnect with data on the
first data element read from the Target read FIFO.
Command/Address Setup
When the Target has accepted a PCI Target transac-
tion, it will inform the FPGA application by asserting the
signal
treqn
. The FPGA can then transfer the PCI start
address, Target command word, and data in the spe-
cific order prescribed in Table 22 through Table 23, for
the operational mode (quad- and dual-port). The
address data is transferred via bus
twdata
(quad-port
mode) or
datatofpga
(dual-port mode with
fifo_sel
= 1) when
taenn
is asserted.
taenn
should
only be asserted when
treqn
is active and
t_ready
is
active. The command/address phase ends with the
assertion of
twlastcycn
. The Target command word
(PCI bus command) and decoded BAR register are
transferred on the separate buses
tcmd
and
bar
,
respectively, and are valid when
treqn
is active.
The number of cycles necessary to send the Target
address can vary. The Target FIFO interface will ana-
lyze the size of the decoded BAR, and performed the
minimal number of cycles to completely transfer the
page of the address. For example, if the BAR is 256K in
size, only the lower 18 bits of address is required by the
FPGA application. This will result in one clock address
transfer for dual-port (32-bits) and two for the quad-port
(16-bits).
Accompanying the address data during the assertion of
taen
, is information on the current Target transaction.
Dual-address or 64-bit address is indicated during the
address phase by
twdata[16]
(quad-port) or
datatofp-
gax
[
0
] (dual-port with
fifo_sel
= 1) being asserted. If
the current transaction is a burst,
twdata[17]
(quad-
port) or
datatofpgax[1]
(dual-port with
fifo_sel
= 1)
will be asserted.
All burst transactions (burst indication bit active) and
64-bit agents (
pci_64bit
= 1) will have the Target data
aligned on a 64-bit address boundary (
ad2
= 0), even if
the PCI start address starts on a 32-bit address with
ad2
= 1. If the burst transaction on the PCI bus starts
on a odd 32-bit address boundary (
ad2
= 1), the data
phase start address will be on a 64-bit address bound-
ary (
ad2
= 0). Likewise, the data phase will also end on
a 64-bit address boundary, therefore the number of
transfers between the Target FIFO interface and the
FPGA application will always be even. For Target read
transactions starting at an odd 32-bit address bound-
ary, the first read data word is ignored by the Target
controller, but needs to be transferred by the FPGA
application.
For single transactions (burst indication bit deasserted)
on a 32-bit bus (
pci_64bit
= 0), the Target FIFO inter-
face will handle all data alignment. The received
address is valid, with the data phase aligning to the
address. No extra data is transferred or padded.
Read Data Transfer
The FPGA application enters the read data phase by
deasserting
taenn
and asserting
trdataenn
. On every
cycle that
trdataenn
is asserted, the FPGA application
provides read data to the Target read FIFO (64-, 32-bit
words; 32-, 64-bit words) via bus
trdata
(quad-port
mode) or
datafmfpga
(dual-port mode).
trdataenn
must not be asserted when the read data FIFOs are full
(
tr_fulln
is asserted). All byte lanes are passed on to
the PCI bus, therefore no byte enables are required.
Note that
tr_fulln
can be updated on the same clock
edge as
trdataenn
is sampled.
The distinction between a burst read and a single
access on a 32-bit bus (
pci_64bit
= 0) is provided by
the burst indication bit,
twdata[17]
(quad-port) or
datatofpgax[1]
(dual-port with
fifo_sel
= 1), along with
the behavior of the
trlastcycn
signal during the data
phase. When
trlastcycn
is asserted, this signal
informs the FPGA application of the end of the read
data phase, and that the Master has disconnected.
trlastcycn
will remain deasserted with every read data
element except the last element on bus
trdata
(quad-
port mode) or
datafmfpga
(dual-port mode).
trlast-
cycn
can remain asserted throughout a single (non-
burst) Target read data phase. on a 32-bit PCI bus
(
pci_64bit
= 0). For example, on a single 32-bit word
transfer in dual-port mode,
trlastcycn
would be
asserted during the entire read data phase, since the
last data phase is the only data phase of this transfer.
After receiving an asserted
trlastcycn
, the FPGA
application should deassert
trdataenn
. For
trlastcycn
to be asserted,
trdataenn
must be asserted.
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