參數資料
型號： OR3TP12
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現場可編程系統(tǒng)芯片（促進文化基金）嵌入式主/目標PCI接口
文件頁數： 43/128頁
文件大?。?/td> 2450K
代理商： OR3TP12
Lucent Technologies Inc.
43
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Master Controller Detailed Description
(continued)
Table 13. Dual-Port Master Writes
1. When
maenn
and
ma_fulln
are deasserted high, the Master interface is idle.
2. When
maenn
is asserted low, a command/address phase is in progress.
3.
maenn
must be asserted low for command/address data to transfer and state to change.
4.
maenn
must be deasserted high and
mwdataenn
must be asserted low to execute the data phase and state to change.
5. Next state = 0 if
mwlastcycn
is asserted low (end of Master write data phase).
6. Next state = A if
mwlastcycn
is asserted low (end of Master command/address phase).
Table 14. Quad-Port Master Writes
1. When
maenn
and
ma_fulln
are deasserted high, the Master interface is idle.
2. When
maenn
is asserted low, a command/address phase is in progress.
3.
maenn
must be asserted low for command/address data to transfer and state to change.
4.
maenn
must be deasserted high and
mwdataenn
must be asserted low to execute the data phase and state to change.
5. Next state = 0 if
mwlastcycn
is asserted low (end of Master write data phase).
6. Next state = 6 if
mwlastcycn
is asserted low (end of Master command/address phase).
MStateCntr
Next State of
MStateCntr
Description
Data on Bus
datafmfpgax[3:0],
datafmfpga[31:0]
XXXX
4
, XXXX
16
Command Word [17:16], XX
2
,
Command Word [15:0], XXXX
16
XXXX
4
, PCIAddress[31:0]
XXXX
4
, PCIAddress[63:32]
BEN[3:0], PCIData[31:0]
BEN[7:4], PCIData[63:32]
Notes
0
0
0
Idle
1
1 or A
Command Word
2, 3, 6
1
2
A
B
2 or A
A
B or 0
A or 0
Address[31:0]
Address[63:32]
Data[31:0]
Data[63:32]
2, 3, 6
2, 3, 6
4, 5
4, 5
MStateCntr
Next State of
MStateCntr
0
1 or 6
2 or 6
3 or 6
4 or 6
6
7
8 or 0
9
6 or 0
Description
Data on Bus
mwdata[17:0]
Notes
0
0
1
2
3
4
6
7
8
9
Idle
XX
2
, XXXX
16
Command Word
XX
2
, PCIAddress[15:0]
XX
2
, PCIAddress[31:16]
XX
2
, PCIAddress[47:32]
XX
2
, PCIAddress[63:48]
BEN[1:0], PCIData[15:0]
BEN[3:2], PCIData[31:16]
BEN[5:4], PCIData[47:32]
BEN[7:6], PCIData[63:48]
1
Command Word
Address[15:0]
Address[31:16]
Address[47:32]
Address[63:48]
Data[15:0]
Data[31:16]
Data[47:32]
Data[63:48]
2, 3, 6
2, 3, 6
2, 3, 6
2, 3, 6
2, 3, 6
4
4, 5
4
4, 5
Master Read Operation
Command/Address Setup
In order to initiate a PCI Master read operation, the
FPGA application must supply the Master command,
Master read burst length, and PCI start address in the
specific order prescribed in Table 15 and Table 17, for
quad- and dual-port mode respectively. The bit defini-
tions of the Master command word are shown in
Table 10. This data is transferred via bus
mwdata
(quad-port mode) or
datafmfpga
(dual-port mode), and
cannot be accepted by the Master FIFO interface
unless
ma_fulln
is inactive and
m_ready
is active. The
Master command word, Master read burst length, and
start address must be accompanied by assertion of the
enable
maenn
, with the command/address phase end-
ing with the assertion of
mwlastcycn
. After the com-
mand/address phase completes,
ma_fulln
goes active
indicating the Master will be begin negotiating for the
PCI bus.
相關PDF資料
PDF描述
OR62 OR62 is a 6-input OR gate with 2x drive strength
OR73 7-input OR gate with 3x drive strength.
OR8GU41 DIFFUSED TYPE (HIGH SPEED RECTIFIER APPLICATIONS)
ORCAORT4622 Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
ORCAORT82G5 1.0?.25/2.0?.5/3.125 Gbits/s Backplane Interface FPSC
相關代理商/技術參數
參數描述
OR3TP12-6BA256 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA256-DB 功能描述:FPGA - 現場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA256I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA256I-DB 功能描述:FPGA - 現場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA352 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*