參數(shù)資料
型號(hào)： OR3TP12
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口
文件頁(yè)數(shù)： 80/128頁(yè)
文件大?。?/td> 2450K
代理商： OR3TP12
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)當(dāng)前第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
80
L Lucent Technologies Inc.
PCI Bus Core Target Controller Detailed
Description
(continued)
Clocking Options at FPGA/Embedded Core
Boundary
The OR3TP12 PCI bus core is divided into two clock
domains by two sets of dual-port FIFOs, one set dedi-
cated to each Target and Master function. The FPGA
supplies at least one clock, while the PCI bus provides
the second clock (
clk
).
The Master and Target FIFOs interface are always
independently clocked on the FPGA side by either
fclk1
or
fclk2
. The clocks used for the Master FIFO
and Target FIFO interfaces to the FPGA application
can be independent when the interface is configured in
quad-port mode, but they must use the same clock sig-
nal for dual-port mode. For dual-port, only one clock
port is active while the other is tied inactive.
All transfers to/from the FIFO interfaces are synchro-
nized to
fclk1
and/or
fclk2
. Which port is used for syn-
chronization is decided by the FPSC configuration
manager for the Master and Target FIFO interfaces.
The ORCAFoundry software will minimize the clock
skew between the FFs involved in the data transfers
and the appropriate synchronized clock port. The clock
delay from the clock source to the
fclk1/2
port usually
does not affect transfer across the Master or Target
FIFO interface, since the interface is referenced from
the clock port (
fclk1
or
fclk2
) and not the clock source
driver.
Figure 34 illustrates the special clock paths provided to
service the clocking needs of OR3TP12. The various
clocking options shown in Figure 34 are discussed
below.
PCI Clock as Interface Clock
The clock received from the PCI bus can be brought
across the embedded core into the FPGA logic section
and used as the clock for the entire OR3TP12, and
even as the clock for the entire board on which the
OR3TP12 resides. It is important that this signal be
obtained via the embedded PCI bus core only since
PCI rules allow for one load per agent on the PCI bus
clock. The OR3TP12 incorporates a clock tree for dis-
tributing the PCI clock; these lines are hard-connected
in the PCI bus core's circuitry and are passed up onto
the FPGA portion's clock grid. From there, the clock
can feed all PFUs, PIOs,
fclk1
,
fclk2
, and off-chip
resources.
Local Clock as Interface Clock
The FIFO interface between the PCI bus core and the
FPGA must use clocks sourced from the FPGA array.
The Master and Target FIFO interfaces each have inde-
pendent clock nets (
fclk1/2
) and can be connected to
the same or separate clocks. Both the Master and Tar-
get FIFO interface can be independently configured to
use any clock located in the FPGA, or provided exter-
nally.
The clocks for the Master and Target FIFO Interface are
fed from specific vertical clock spines, namely, the
spines in PLC columns five and 13. Consequently, min-
imum clock net delay is obtained by feeding external
clocks from I/O pads in locations on the top of the array
near these splines. Depending on which spline (
fclk1
or
fclk2
) is used to distribute the clock to the Master
and Target FIFO Interface, it is recommended to use a
PIO that lies in that same column as the spline. For
fclk1
(which lies in column 13), use a PIO in PT13A-
PT14D. For
fclk2
(which lies in column five), use a PIO
in PT5A-PT6D. If the user chooses the FAST_CLOCK
or EXPRESS_CLOCK as a source for the OR3TP12
clock, additional clock delay may be introduced. Never-
theless, clocks can be fed from any I/O pad, from
express clock inputs, or from internal logic, and can be
fed via the PCM.
相關(guān)PDF資料
PDF描述
OR62 OR62 is a 6-input OR gate with 2x drive strength
OR73 7-input OR gate with 3x drive strength.
OR8GU41 DIFFUSED TYPE (HIGH SPEED RECTIFIER APPLICATIONS)
ORCAORT4622 Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
ORCAORT82G5 1.0?.25/2.0?.5/3.125 Gbits/s Backplane Interface FPSC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3TP12-6BA256 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA256-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA256I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA256I-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA352 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*