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參數(shù)資料
| 型號： | BX80524R300128 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, MICROPROCESSOR, XMA |
| 封裝： | SINGLE EDGE PROCESSOR PACKAGE |
| 文件頁數(shù)： | 85/130頁 |
| 文件大?。?/td> | 2654K |
| 代理商： | BX80524R300128 |
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58
Datasheet
Intel Celeron Processor up to 1.10 GHz
3.3.2
Ringback Specification
Ringback refers to the amount of reflection seen after a signal has switched. The ringback
specification is the voltage that the signal rings back to after achieving its maximum absolute
value. (See Figure 14 for an illustration of ringback.) Excessive ringback can cause false signal
detection or extend the propagation delay. The ringback specification applies to the input pin of
each receiving agent. Violations of the signal ringback specification are not allowed under any
circumstances for non-AGTL+ signals.
Ringback can be simulated with or without the input protection diodes that can be added to the
input buffer model. However, signals that reach the clamping voltage should be evaluated further.
See Table 34 for the signal ringback specifications for non-AGTL+ signals for simulations at the
lists the ringback specifications for the FC-PGA/FC-PGA2 packages.
NOTE:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
NOTE:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all FC-PGA/FC-PGA2 processor frequencies
and cache sizes.
Table 34. Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor
Core (S.E.P. and PPGA Packages)
Input Signal Group
Transition
Maximum Ringback
(with Input Diodes Present)
Unit
Figure
Notes
Non-AGTL+ Signals
0
→ 11.7
V
Non-AGTL+ Signals
1
→ 00.7
V
Table 35. Signal Ringback Guidelines for Non-AGTL+ Signal Edge Finger Measurement
(S.E.P. Package)
Input Signal Group
Transition
Maximum Ringback
(with Input Diodes Present)
Unit
Figure
Notes
Non-AGTL+ Signals
0
→ 12.0
V
Non-AGTL+ Signals
1
→ 00.7
V
Table 36. Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor
Pins (FC-PGA/FC-PGA2 Packages)
Input Signal Group
Transition
Maximum Ringback
(with Input Diodes Present)
Unit
Figure
Non-AGTL+ Signals
0
→ 1VREF + 0.200
V
PWRGOOD
0
→ 12.0
V
Non-AGTL+ Signals
1
→ 0VREF – 0.200
V
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