參數(shù)資料
型號(hào)： BX80524R300128
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 300 MHz, MICROPROCESSOR, XMA
封裝： SINGLE EDGE PROCESSOR PACKAGE
文件頁數(shù)： 79/130頁
文件大?。?/td> 2654K
代理商： BX80524R300128
52
Datasheet
Intel Celeron Processor up to 1.10 GHz
3.0
System Bus Signal Simulations
Signals driven on the Celeron processor system bus should meet signal quality specifications to
ensure that the components read data properly and to ensure that incoming signals do not affect the
long term reliability of the component. Specifications are provided for simulation at the processor
core; guidelines are provided for correlation to the processor edge fingers. These edge finger
guidelines are intended for use during testing and measurement of system signal integrity.
Violations of these guidelines are permitted, but if they occur, simulation of signal quality at the
processor core should be performed to ensure that no violations of signal quality specifications
occur. Meeting the specifications at the processor core in Table 28, Table 31, and Table 34 ensures
that signal quality effects will not adversely affect processor operation, but does not necessarily
guarantee that the guidelines in Table 30, Table 33, and Table 35 will be met.
3.1
System Bus Clock (BCLK) Signal Quality Specifications
and Measurement Guidelines
Table 28 describes the BCLK signal quality specifications at the processor core for both S.E.P. and
PPGA Packages. Table 29 shows the BCLK and PICCLK signal quality specifications at the
processor core for the FC-PGA/FC-PGA2 packages. Table 30 describes guidelines for signal
quality measurement at the processor edge fingers. Figure 11 describes the signal quality waveform
for the system bus clock at the processor core pins; Figure 12 describes the signal quality
waveform for the system bus clock at the processor edge fingers.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. This is the Intel Celeron processor system bus clock overshoot and undershoot specification for 66 MHz
system bus operation.
3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This
specification is an absolute value.
Table 28. BCLK Signal Quality Specifications for Simulation at the Processor Core
(for Both S.E.P. and PPGA Packages)
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
V1: BCLK VIL
0.5
V
V2: BCLK VIH
2.0
V
2
V3: VIN Absolute Voltage Range
–0.7
3.5
V
2
V4: Rising Edge Ringback
1.7
V
3
V5: Falling Edge Ringback
0.7
V
3
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