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參數(shù)資料
| 型號： | BX80524R300128 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, MICROPROCESSOR, XMA |
| 封裝： | SINGLE EDGE PROCESSOR PACKAGE |
| 文件頁數(shù)： | 74/130頁 |
| 文件大?。?/td> | 2654K |
| 代理商： | BX80524R300128 |
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48
Datasheet
Intel Celeron Processor up to 1.10 GHz
Note:
For Figure 3 through Figure 10, the following apply:
2. All AC timings for the AGTL+ signals at the processor edge fingers are referenced to the
BCLK rising edge at 0.50 V. This reference is to account for trace length and capacitance on
the processor substrate, allowing the processor core to receive the signal with a reference at
1.25 V. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the
processor edge fingers.
3. All AC timings for the AGTL+ signals at the processor core pins are referenced to the BCLK
rising edge at 1.25 V. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at
1.00 V at the processor core pins.
4. All AC timings for the CMOS signals at the processor edge fingers are referenced to the
BCLK rising edge at 0.50 V. This reference is to account for trace length and capacitance on
the processor substrate, allowing the processor core to receive the signal with a reference at
1.25 V. All CMOS signal timings (compatibility signals, etc.) are referenced at 1.25 V at the
processor edge fingers.
5. All AC timings for the APIC I/O signals at the processor edge fingers are referenced to the
PICCLK rising edge at: 0.7 V for S.E.P. and PPGA packages and 0.75 V for the FC-PGA/
FC-PGA2 packages. All APIC I/O signal timings are referenced at 1.25 V for S.E.P. and
PPGA packages and 0.75 V for the FC-PGA/FC-PGA2 packages at the processor edge
fingers.
6. All AC timings for the TAP signals at the processor edge fingers are referenced to the TCK
rising edge at 0.70 V for S.E.P. and PPGA packages and 0.75 V for the FC-PGA/FC-PGA2
packages. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V for S.E.P. and
PPGA packages and 0.75 V for the FC-PGA/FC-PGA2 packages at the processor edge
fingers.
Figure 2. BCLK to Core Logic Offset
BCLK at
Edge Fingers
0.5V
BCLK at
Core Logic
1.25V
T1B'
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