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參數(shù)資料
| 型號(hào)： | BX80524R300128 |
| 廠商： | INTEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, MICROPROCESSOR, XMA |
| 封裝： | SINGLE EDGE PROCESSOR PACKAGE |
| 文件頁(yè)數(shù)： | 46/130頁(yè) |
| 文件大?。?/td> | 2654K |
| 代理商： | BX80524R300128 |
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22
Datasheet
Intel Celeron Processor up to 1.10 GHz
open drain and should be pulled high to VCCCMOS. This ensures not only correct operation for
current Intel Celeron processors, but compatibility for future Intel Celeron processor products as
well.
The groups and the signals contained within each group are shown in Table 3. Refer to Section 7.0
for descriptions of these signals.
NOTES:
1. See Section 7.0 for information on the PWRGOOD signal.
2. See Section 7.0 for information on the SLP# signal.
3. See Section 7.0 for information on the THERMTRIP# signal.
4. These signals are specified for 2.5 V operation for S.E.P.P. and PPGA packages; they are specified at 1.5V
operation for the FC-PGA/FC-PGA2 packages.
5. VCCCORE is the power supply for the processor core.
VID[4:0] and VID[3:0] are described in Section 2.0.
VTT is used to terminate the system bus and generate VREF on the processor substrate.
VSS is system ground.
VCC5 is not connected to the Celeron processor. This supply is used for Voltage Transient Tools.
SLOTOCC# is described in Section 7.0.
BSEL is described in Section 2.7.2 and Section 7.0.
EMI pins are described in Section 7.0.
VCCL2 is a Pentium
II processor reserved signal provided to maintain compatibility with the Pentium II
processor and may be left as a no-connect for “Intel Celeron processor-only” designs.
6. Only applies to Intel Celeron processors in the S.E.P. Package.
7. Only applies to Intel Celeron processors in the PPGA and FC-PGA/FC-PGA2 packages.
8. The BR0# pin is the only BREQ# signal that is bidirectional. See Section 7.0 for more information.
9. These signals are specified for 2.5 V operation.
10.BSEL1 is not used in Celeron processors.
11. RESET# must always be terminated to VTT on the motherboard for PGA packages. On-die termination is not
provided for this signal on FC-PGA/FC-PGA2 packages.
12.For the FC-PGA/FC-PGA2 packages, this signal is used to control the value of the processor on-die
termination resistance. Refer to the specific platform design guide for the recommended pull-down resistor
value.
13.Only applies to Intel Celeron processors in the FC-PGA/FC-PGA2 packages.
14.S.E.P. Package and FC-PGA/FC-PGA2 packages.
Table 3.
Intel Celeron Processor System Bus Signal Groups
Group Name
Signals
AGTL+ Input
BPRI#, DEFER#, RESET#11, RS[2:0]#, TRDY#
AGTL+ Output
PRDY#
AGTL+ I/O
A[31:3]#, ADS#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#8, D[63:0]#, DBSY#, DRDY#, HIT#,
HITM#, LOCK#, REQ[4:0]#,
CMOS Input4
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI#, SLP#2,
STPCLK#
CMOS Input
PWRGOOD1,9
CMOS Output4
FERR#, IERR#, THERMTRIP#3
System Bus Clock
BCLK9
APIC Clock
PICCLK9
APIC I/O4
PICD[1:0]
TAP Input4
TCK, TDI, TMS, TRST#
TAP Output4
TDO
Power/Other5
CPUPRES#7, EDGCTRL7, EMI6, PLL[2:1]7, SLOTOCC#6, THERMDP, THERMDN,
VCC1.5
7, VCC
2.5
7, VCC
L2
5, VCC
5
6, VCC
CMOS
7, VCC
CORE, VCOREDET
7, VID[3:0]7,
VID[4:0]6, VREF[7:0]7, VSS, VTT14, RTTCTRL12, BSEL[1:0]10, SLEWCTRL13
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