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參數資料
| 型號： | BX80524R300128 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, MICROPROCESSOR, XMA |
| 封裝： | SINGLE EDGE PROCESSOR PACKAGE |
| 文件頁數： | 29/130頁 |
| 文件大?。?/td> | 2654K |
| 代理商： | BX80524R300128 |
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124
Datasheet
Intel Celeron Processor up to 1.10 GHz
REQ[4:0]#
I/O
The REQ[4:0]# (Request Command) signals must connect the appropriate pins of
all processor system bus agents. They are asserted by the current bus owner over
two clock cycles to define the currently active transaction type.
RESET#
I
Asserting the RESET# signal resets the processor to a known state and invalidates
the L1 cache without writing back any of the contents. RESET# must stay active for
at least one millisecond after VCCCORE and CLK have reached their proper
specifications. On observing active RESET#, all system bus agents will deassert
their outputs within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the
Pentium Pro Family Developer’s Manual, Volume 1: Specifications
(Order Number
242690).
The processor may have its outputs tristated via power-on configuration. Otherwise,
if INIT# is sampled active during the active-to-inactive transition of RESET#, the
processor will execute its Built-in Self-Test (BIST). Whether or not BIST is executed,
the processor will begin program execution at the power on Reset vector (default
0_FFFF_FFF0h). RESET# must connect the appropriate pins of all processor
system bus agents.
RS[2:0]#
I
The RS[2:0]# (Response Status) signals are driven by the response agent (the
agent responsible for completion of the current transaction), and must connect the
appropriate pins of all processor system bus agents.
RTTCTRL
I
The RTTCTRL input signal provides AGTL+ termination control. The Celeron
FC-PGA/FC-PGA2 processor samples this input to sense the presence of
motherboard AGTL+ termination. See the platform design guide for implementation
details.
SLEWCTRL
I
The SLEWCTRL input signal provides AGTL+ slew rate control. The Celeron
FC-PGA/FC-PGA2 processor samples this input to determine the slew rate for
AGTL+ signals when it is the driving agent. See the platform design guide for
implementation details.
SLOTOCC#
(S.E.P.P. only)
O
SLOTOCC# is defined to allow a system design to detect the presence of a
terminator card or processor in a SC242 connector. This pin is not a signal; rather, it
is a short to VSS. Combined with the VID combination of VID[4:0]= 11111 (see
Section 2.5), a system can determine if a SC242 connector is occupied, and
whether a processor core is present. The states and values for determining the type
of cartridge in the SC242 connector is shown below.
SLP#
I
The SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors to
enter the Sleep state. During Sleep state, the processor stops providing internal
clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor will
recognize only assertions of the SLP#, STPCLK#, and RESET# signals while in
Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to
Stop-Grant state, restarting its internal clock signals to the bus and APIC processor
core units.
Table 59. Alphabetical Signal Reference (Sheet 5 of 7)
Signal
Type
Description
SC242 Occupation Truth Table
Signal
Value
Status
SLOTOCC#
VID[4:0]
0
Anything other than ‘11111’
Processor with core in SC242
connector.
SLOTOCC#
VID[4:0]
0
11111
Terminator cartridge in SC242
connector (i.e., no core present).
SLOTOCC#
VID[4:0]
1
Any value
SC242 connector not occupied.
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