參數(shù)資料
型號： BX80524R300128
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 300 MHz, MICROPROCESSOR, XMA
封裝： SINGLE EDGE PROCESSOR PACKAGE
文件頁數(shù)： 76/130頁
文件大小： 2654K
代理商： BX80524R300128
Datasheet
5
Intel Celeron Processor up to 1.10 GHz
Figures
Clock Control State Machine............................................................................... 16
BCLK to Core Logic Offset ..................................................................................48
BCLK*, PICCLK, and TCK Generic Clock Waveform ......................................... 49
System Bus Valid Delay Timings ........................................................................ 49
System Bus Setup and Hold Timings.................................................................. 49
System Bus Reset and Configuration Timings (For the S.E.P. and
PPGA Packages) ................................................................................................ 50
System Bus Reset and Configuration Timings (For the
FC-PGA/FC-PGA2 Package) .............................................................................. 50
Power-On Reset and Configuration Timings....................................................... 51
Test Timings (TAP Connection) .......................................................................... 51
Test Reset Timings ............................................................................................. 51
BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins .....53
BCLK, TCK, PICCLK Generic Clock Waveform at the Processor
Edge Fingers ....................................................................................................... 54
Low to High AGTL+ Receiver Ringback Tolerance............................................. 56
Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback ..................... 57
Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback .................... 64
Processor Functional Die Layout (CPUID 0686h)............................................... 67
Processor Functional Die Layout (up to CPUID 0683h)...................................... 67
Processor Substrate Dimensions (S.E.P. Package) ........................................... 70
Processor Substrate Primary/Secondary Side Dimensions (S.E.P. Package).... 70
S.E.P. Package ................................................................................................. 111
Boxed Intel Celeron Processor in the PPGA Package .................................. 113
370-Pin Socket (FC-PGA/FC-PGA2 Packages)................................................114
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