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參數(shù)資料
| 型號(hào)： | BX80524R300128 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, MICROPROCESSOR, XMA |
| 封裝： | SINGLE EDGE PROCESSOR PACKAGE |
| 文件頁(yè)數(shù)： | 13/130頁(yè) |
| 文件大小： | 2654K |
| 代理商： | BX80524R300128 |
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Datasheet
11
Intel Celeron Processor up to 1.10 GHz
1.0
Introduction
The Intel Celeron processor is based on the P6 microarchitecture and is optimized for the Value
PC market segment. The Intel Celeron processor, like the Pentium
II processor, features a
Dynamic Execution microarchitecture and executes MMX technology instructions for enhanced
media and communication performance. The Intel Celeron processor also utilizes multiple low-
power states such as AutoHALT, Stop-Grant, Sleep, and Deep Sleep to conserve power during idle
times.
The Intel Celeron processor is capable of running today’s most common PC applications with up to
4 GB of cacheable memory space. As this processor is intended for Value PC systems, it does not
provide multiprocessor support. The Pentium II and Pentium
III processors should be used for
multiprocessor system designs.
To be cost-effective at both the processor and system level, the Intel Celeron processor utilizes
cost-effective packaging technologies. They are the S.E.P. (Single-Edge Processor) package, the
PPGA (Plastic Pin Grid Array) package, the FC-PGA (Flip-Chip Pin Grid Array) package, and the
FC-PGA2 (Flip-Chip Pin Grid Array) package. Refer to the Intel Celeron Processor
Specification Update for the latest packaging and frequency support information (Order Number
243337).
Note:
This datasheet describes the Intel Celeron processor for the PPGA package, FC-PGA/FC-PGA2
packages, and the S.E.P. Package versions. Unless otherwise specified, the information in this
document applies to all versions and information on PGA packages, refer to both PPGA and
FC-PGA packages.
1.1
Terminology
In this document, a ‘#’ symbol after a signal name refers to an active low signal. This means that a
signal is in the active state (based on the name of the signal) when driven to a low level. For
example, when FLUSH# is low, a flush has been requested. When NMI is high, a nonmaskable
interrupt has occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal
is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to
a hex ‘A’ (H= High logic level, L= Low logic level).
The term “system bus” refers to the interface between the processor, system core logic (a.k.a. the
AGPset components), and other bus agents. The system bus is an interface to the processor,
memory, and I/O.
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