參數(shù)資料
型號(hào): TSB82AA2I
廠商: Texas Instruments, Inc.
英文描述: 1394b OHCI-LYNX CONTROLLER
中文描述: 的1394b OHCI的山貓控制器
文件頁(yè)數(shù): 94/104頁(yè)
文件大?。?/td> 461K
代理商: TSB82AA2I
56
5.6
Timestamp Offset Register
The value of this register is added as an offset to the cycle timer value when using the MPEG, DV, and CIP
enhancements. A timestamp offset register is implemented per isochronous transmit context. The n value following
the offset indicates the context number (n = 0, 1, 2, 3,
, 7). These registers are programmed by software as
appropriate. See Table 54 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Timestamp offset
Type
R/W
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Timestamp offset
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Timestamp offset
A90h + (4*n)
Read/Write, Read-only
0000 0000h
Table 54. Timestamp Offset Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
DisableInitialOffset
R/W
Bit 31 disables the use of the initial timestamp offset when the MPEG2 enhancements are enabled.
A value of 0 indicates the use of the initial offset, a value of 1 indicates that the initial offset must not
be applied to the calculated timestamp. This bit has no meaning for the DV timestamp
enhancements.
3025
RSVD
R
Reserved. Bits 3025 return 0s when read.
2412
CycleCount
R/W
This field adds an offset to the cycle count field in the timestamp when the DV or MPEG2
enhancements are enabled. The cycle count field is incremented modulo 8000; therefore, values in
this field must be limited between 0 and 7999.
110
CycleOffset
R/W
This field adds an offset to the cycle offset field in the timestamp when the DV or MPEG2
enhancements are enabled. The cycle offset field is incremented modulo 3072; therefore, values in
this field must be limited between 0 and 3071.
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