![](http://datasheet.mmic.net.cn/370000/TSB82AA2I_datasheet_16739965/TSB82AA2I_63.png)
421
4.22 Interrupt Mask Register
The interrupt mask set/clear register enables the various TSB82AA2 interrupt sources. Reads from either the set
register or the clear register always return the contents of the interrupt mask register. In all cases except bit 31
(masterIntEnable) and bit 30 (VendorSpecific), the enables for each interrupt event align with the interrupt event
register bits detailed in Table 416.
This register is fully compliant with
1394 Open Host Controller Interface Specification
, and the TSB82AA2 device
adds a vendor-specific interrupt function to bit 30. See Table 417 for a description of bits 31 and 30.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Interrupt mask
Type
RSCU
RSC
RSC
R
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
Default
X
X
0
0
0
X
X
X
X
X
X
X
X
0
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Interrupt mask
Type
RSC
R
R
R
R
R
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
Default
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
Register:
Type:
Offset:
Interrupt mask
Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only
88h
set register
8Ch
clear register
XXXX 0XXXh
Default:
Table 417. Interrupt Mask Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
masterIntEnable
RSCU
Master interrupt enable. If bit 31 is set to 1, then the external interrupts are generated in accordance
with the interrupt mask register. If bit 31 is cleared, then the external interrupts are not generated
regardless of the interrupt mask register settings.
30
VendorSpecific
RSC
When this bit and bit 30 (vendorSpecific) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21,
Interrupt Event Register
) are set to 1, this vendor-specific interrupt mask enables
interrupt generation.
29
SoftInterrupt
RSC
When this bit and bit 29 (SoftInterrupt) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21,
Interrupt Event Register
) are set to 1, this soft-interrupt mask enables interrupt
generation.
28
RSVD
R
Reserved. Bit 28 returns 0 when read.
27
ack_tardy
RSC
When this bit and bit 27 (ack_tardy) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21,
Interrupt Event Register
) are set to 1, this acknowledge-tardy interrupt mask enables
interrupt generation.
26
phyRegRcvd
RSC
When this bit and bit 26 (phyRegRcvd) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21,
Interrupt Event Register
) are set to 1, this PHY-register interrupt mask enables interrupt
generation.
25
cycleTooLong
RSC
When this bit and bit 25 (cycleTooLong) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21,
Interrupt Event Register
) are set to 1, this cycle-too-long interrupt mask enables
interrupt generation.
24
unrecoverableError
RSC
When this bit and bit 24 (unrecoverableError) in the interrupt event register at OHCI offset 80h/84h
(see Section 4.21,
Interrupt Event Register
) are set to 1, this unrecoverable-error interrupt mask
enables interrupt generation.
23
cycleInconsistent
RSC
When this bit and bit 23 (cycleInconsistent) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21,
Interrupt Event Register
) are set to 1, this inconsistent-cycle interrupt mask enables
interrupt generation.
22
cycleLost
RSC
When this bit and bit 22 (cycleLost) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21,
Interrupt Event Register
) are set to 1, this lost-cycle interrupt mask enables interrupt
generation.