![](http://datasheet.mmic.net.cn/370000/TSB82AA2I_datasheet_16739965/TSB82AA2I_40.png)
320
Table 322. Link Enhancement Control Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
1312
atx_thresh
R/W
This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the
TSB82AA2 device retries the packet, it uses a 2K-byte threshold resulting in a store-and-forward
operation.
00 = Threshold ~ 4K bytes resulting in a store-and-forward operation (default)
01 = Threshold ~ 1.7K bytes
10 = Threshold ~ 1K bytes
11 = Threshold ~ 512 bytes
These bits fine-tune the asynchronous transmit threshold. Changing this value may increase or
decrease the 1394 latency depending on the average PCI bus latency.
Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds
or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than
the AT threshold, then the remaining data must be received before the AT FIFO is emptied; otherwise,
an underrun condition occurs, resulting in a packet error at the receiving node. As a result, the link then
commences store-and-forward operation—that is, wait until it has the complete packet in the FIFO
before retransmitting it on the second attempt, to ensure delivery.
An AT threshold of 4K results in store-and-forward operation, which means that asynchronous data
is not transmitted until an end-of-packet token is received. Restated, setting the AT threshold to 4K
results in only complete packets being transmitted.
Note that this device always uses store-and-forward when the asynchronous transmit retries register
at OHCI offset 08h (see Section 4.3,
Asynchronous Transmit Retries Register
) is cleared.
1110
RSVD
R
Reserved. Bits 1110 return 0s when read.
9
enab_aud_ts
R/W
Enable audio/music CIP timestamp enhancement. When bit 9 is set to 1, the enhancement is enabled
for audio/music CIP transmit streams (FMT = 10h).
8
enab_dv_ts
R/W
Enable DV CIP timestamp enhancement. When bit 8 is set to 1, the enhancement is enabled for DV
CIP transmit streams (FMT = 00h).
7
enab_unfair
R/W
Enable asynchronous priority requests. OHCI-Lynx compatible. Setting bit 7 to 1 enables the link to
respond to requests with priority arbitration. It is recommended that this bit be set to 1.
6
RSVD
R
Bit 6 is not assigned in the TSB82AA2 follow-on products since this location, which is loaded by the
serial EEPROM from the enhancements field, corresponds to bit 23 (programPhyEnable) in the host
controller control register at OHCI offset 50h/54h (see Section 4.16,
Host Controller Control Register
).
53
RSVD
R
Reserved. Bits 53 return 0s when read.
2
enab_insert_idle
R/W
Enable insert idle. OHCI-Lynx compatible. When the PHY device has control of the
PHY_CTL0PHY_CTL1 control lines and PHY_DATA0PHY_DATA7 data lines and the link requests
control, the PHY device drives 11b on the PHY_CTL0PHY_CTL1 lines. The link can then start driving
these lines immediately. Setting bit 2 to 1 inserts an idle state, so the link waits one clock cycle before
it starts driving the lines (turnaround time).
1
enab_accel
R/W
Enable acceleration enhancements. OHCI-Lynx compatible. When bit 1 is set to 1, the PHY device
is notified that the link supports the IEEE Std 1394a-2000 acceleration enhancements, that is,
ack-accelerated, fly-by concatenation, etc. It is recommended that bit 1 be set to 1.
0
RSVD
R
Reserved. Bit 0 returns 0 when read.