![](http://datasheet.mmic.net.cn/370000/TSB82AA2I_datasheet_16739965/TSB82AA2I_61.png)
419
4.21 Interrupt Event Register
The interrupt event set/clear register reflects the state of the various TSB82AA2 interrupt sources. The interrupt bits
are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the
set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register.
This register is fully compliant with
1394 Open Host Controller Interface Specification
, and the TSB82AA2 device
adds a vendor-specific interrupt function to bit 30. When the interrupt event register is read, the return value is the
bit-wise AND function of the interrupt event and interrupt mask registers. See Table 416 for a complete description
of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Interrupt event
Type
R
RSC
RSC
R
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
Default
0
X
0
0
0
X
X
X
X
X
X
X
X
0
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Interrupt event
Type
RSCU
R
R
R
R
R
RSCU
RSCU
RU
RU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
Default
0
0
0
Interrupt event
Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only
80h
set register
84h
clear register [returns the content of the interrupt event register bit-wise ANDed with
the interrupt mask register when read]
XXXX 0XXXh
Table 416. Interrupt Event Register Description
0
0
0
X
X
X
X
X
X
X
X
X
X
Register:
Type:
Offset:
Default:
BIT
FIELD NAME
TYPE
DESCRIPTION
31
RSVD
R
Reserved. Bit 31 returns 0 when read.
30
vendorSpecific
RSC
This vendor-specific interrupt event is reported when either of the general-purpose interrupts are
asserted. The general-purpose interrupts are enabled by setting the corresponding bits INT_3EN
and INT_2EN (bits 31 and 23, respectively) to 1 in the GPIO control register at offset FCh in the PCI
configuration space (see Section 3.26,
GPIO Control Register
).
29
SoftInterrupt
RSC
Software interrupt. Bit 29 is used by software to generate a TSB82AA2 interrupt for its own use.
28
RSVD
R
Reserved. Bit 28 returns 0 when read.
27
ack_Tardy
RSCU
Bit 27 is set to 1 when bit 29 (ack_Tardy_enable) in the host controller control register at OHCI offset
50h/54h (see Section 4.16,
Host Controller Control Register
) is set to 1 and any of the following
conditions occur:
a. Data is present in the receive FIFO that is to be delivered to the host.
b. The physical response unit is busy processing requests or sending responses.
c. The TSB82AA2 device sent an ack_tardy acknowledgement.
26
phyRegRcvd
RSCU
The TSB82AA2 device has received a PHY register data byte which can be read from bits 2316 in
the PHY layer control register at OHCI offset ECh (see Section 4.33,
PHY Layer Control Register
).
25
cycleTooLong
RSCU
If bit 21 (cycleMaster) in the link control register at OHCI offset E0h/E4h (see Section 4.31,
Link
Control Register
) is set to 1, then this indicates that over 125
μ
s have elapsed between the start of
sending a cycle start packet and the end of a subaction gap. Bit 21 (cycleMaster) in the link control
register is cleared by this event.
24
unrecoverableError
RSCU
This event occurs when the TSB82AA2 device encounters any error that forces it to stop operations
on any or all of its subunits, for example, when a DMA context sets its dead bit to 1. While bit 24 is
set to 1, all normal interrupts for the context(s) that caused this interrupt are blocked from being set
to 1.
23
cycleInconsistent
RSCU
A cycle start was received that had values for cycleSeconds and cycleCount fields that are different
from the values in bits 3125 (cycleSeconds field) and bits 2412 (cycleCount field) in the
isochronous cycle timer register at OHCI offset F0h (see Section 4.34,
Isochronous Cycle Timer
Register
).