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參數(shù)資料
| 型號： | TSB82AA2I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1394b OHCI-LYNX CONTROLLER |
| 中文描述： | 的1394b OHCI的山貓控制器 |
| 文件頁數(shù)： | 17/104頁 |
| 文件大?。?/td> | 461K |
| 代理商： | TSB82AA2I |
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25
Table 25. 32-Bit PCI Bus Terminals
TERMINAL
I/O
DESCRIPTION
NAME
NO.
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
17
18
19
20
23
24
25
26
29
30
33
34
35
36
37
38
51
53
54
56
57
58
59
60
64
65
66
67
68
69
70
71
I/O
PCI address/data bus for the lower DWORD. These signals make up the multiplexed PCI address and data
bus for the lower 32 bits on the PCI interface. During the address phase of a PCI cycle, AD31AD0 contain a
32-bit address or other destination information. During the data phase, AD31AD0 contain data.
PCI_C/BE0
PCI_C/BE1
PCI_C/BE2
PCI_C/BE3
61
50
39
27
I/O
PCI bus commands and byte enables for lower DWORD. The command and byte enable signals are
multiplexed on the same PCI terminals. During the address phase of a bus cycle, PCI_C/BE3PCI_C/BE0
define the bus command. During the data phase, this 4-bit bus is used as byte enables for the lower 32 bits of
data.
PCI_CLK
10
I
PCI bus clock. Provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge
of PCI_CLK.
PCI_DEVSEL
45
I/O
PCI device select. The TSB82AA2 device asserts this signal to claim a PCI cycle as the target device. As a PCI
initiator, the TSB82AA2 device monitors this signal until a target responds. If no target responds before time-out
occurs, then the TSB82AA2 device terminates the cycle with an initiator abort.
PCI_FRAME
40
I/O
PCI cycle frame. This signal is driven by the initiator of a PCI bus cycle. PCI_FRAME is asserted to indicate
that a bus transaction is beginning, and data transfers continue while this signal is asserted. When PCI_FRAME
is deasserted, the PCI bus transaction is in the final data phase.
PCI_GNT
12
I
PCI bus grant. This signal is driven by the PCI bus arbiter to grant the TSB82AA2 device access to the PCI bus
after the current data transaction has completed. This signal may or may not follow a PCI bus request,
depending upon the PCI bus parking algorithm.
PCI_IDSEL
28
I
Initialization device select. PCI_IDSEL selects the TSB82AA2 device during configuration space accesses.
PCI_IDSEL can be connected to 1 of the upper 24 PCI address lines on the PCI bus.
PCI_INTA
5
O
Interrupt signal. This output indicates interrupts from the TSB82AA2 device to the host. This terminal is
implemented as open-drain.
PCI_IRDY
41
I/O
PCI initiator ready. PCI_IRDY indicates the ability of the PCI bus initiator to complete the current data phase
of the transaction. A data phase is completed upon a rising edge of PCI_CLK where both PCI_IRDY and
PCI_TRDY are asserted.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TSB82AA2IPGE | 功能描述:接口 - 專用 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
| TSB82AA2IPGEEP | 功能描述:1394 接口集成電路 Mil Enh 1394b OHCI- Lynx Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB82AA2PGE | 功能描述:1394 接口集成電路 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB82AA2PGEG4 | 功能描述:1394 接口集成電路 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB82AA2ZGW | 功能描述:1394 接口集成電路 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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