參數(shù)資料
型號(hào)： TSB82AA2I
廠商： Texas Instruments, Inc.
英文描述： 1394b OHCI-LYNX CONTROLLER
中文描述： 的1394b OHCI的山貓控制器
文件頁(yè)數(shù)： 38/104頁(yè)
文件大?。?/td> 461K
代理商： TSB82AA2I
318
3.23 Miscellaneous Configuration Register
The miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 321 for a
complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Miscellaneous configuration
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Miscellaneous configuration
Type
R/W
R
R
R
R
R/W
R/W
R/W
R
R/W
R
R/W
R
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Register:
Type:
Offset:
Default:
Miscellaneous configuration
Read/Write, Read-only
F0h
0000 0010h
Table 321. Miscellaneous Configuration Register
BIT
FIELD NAME
TYPE
DESCRIPTION
3116
RSVD
R
Reserved. Bits 3116 return 0s when read.
15
PME_D3COLD
R/W
PCI_PME support from D3cold. This bit programs bit 15 (PME_D3COLD) in the power
management capabilities register at offset 46h in the PCI configuration space (see Section 3.19,
Power Management Capabilities Register
).
1411
RSVD
R
Reserved. Bits 1411 return 0s when read.
10
Ignore
IntMask.masterInt
Enable_for_pme
R/W
Ignore IntMask.masterIntEnable for PME generation. When set to 1, this bit causes PME
generation behavior to be changed. Also, when set to 1, this bit causes bit 26 of the OHCI
vendor ID register at OHCI offset 40h to read 1; otherwise, bit 26 reads 0.
0 = PME behavior generated from unmasked interrupt bits and bit 31 (masterIntEnable) in the
interrupt mask register at OHCI offset 88h (see Section 4.22,
Interrupt Mask Register
)
(default)
1 = PME behavior does not depend on the value of bit 31 (masterIntEnable)
98
MR_ENHANCE
R/W
This field selects the read command behavior of the PCI master.
00 = Memory read line (default)
01 = Memory read
10 = Memory read multiple
11 = Reserved
7
RSVD
R
Reserved. Bit 7 returns 0 when read.
6
CARDBUS
R/W
CardBus. When bit 6 is set to 1, CardBus register support is enabled, that is, the CardBus base
register and CardBus CIS pointer are valid. Bit 6 is only set if a serial EEPROM is present and
contains a valid CIS. If bit 6 is set to 1, then a valid CIS must be implemented in the EEPROM at
an offset pointed to in EEPROM word 0x14, bits 73.
5
RSVD
R
Reserved. Bit 5 returns 0 when read.
4
DIS_TGT_ABT
R/W
Bit 4 defaults to 1 disabling the target abort behavior when accesses are made to PHY clock
domain registers when no clock is present. Bit 4 can be set to 0 to provide OHCI-Lynx
compatible target abort signaling. When this bit is set to 1, it enables the no-target-abort mode, in
which the TSB82AA2 device returns indeterminate data instead of signaling target abort.
The TSB82AA2 LLC is divided into the PCI_CLK and SCLK domains. If software tries to access
registers in the link that are not active because the SCLK is disabled, then a target abort is
issued by the link. On some systems, this can cause a problem resulting in a fatal system error.
Enabling this bit allows the link to respond to these types of requests by returning FFh.
It is recommended that this bit be set to 1.
Reserved. Bit 3 returns 0 when read.
3
RSVD
R
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