參數(shù)資料
型號： TSB82AA2I
廠商： Texas Instruments, Inc.
英文描述： 1394b OHCI-LYNX CONTROLLER
中文描述： 的1394b OHCI的山貓控制器
文件頁數(shù)： 51/104頁
文件大?。?/td> 461K
代理商： TSB82AA2I
49
4.9
Bus Options Register
The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 47 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Bus options
Type
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
0
0
0
0
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Bus options
Type
R/W
R/W
R/W
R/W
R
R
R
R
R/W
R/W
R
R
R
R
R
R
Default
1
0
1
1
0
0
0
0
X
X
0
0
0
0
1
0
Register:
Type:
Offset:
Default:
Bus options
Read/Write, Read-only
20h
X0XX B0X2h
Table 47. Bus Options Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
irmc
R/W
Isochronous resource-manager capable. IEEE 1394 bus-management field. Must be valid when bit 17
(linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16,
Host
Controller Control Register
) is set to 1.
30
cmc
R/W
Cycle master capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the
host controller control register at OHCI offset 50h/54h (see Section 4.16,
Host Controller Control
Register
) is set to 1.
29
isc
R/W
Isochronous support capable. IEEE 1394 bus-management field. Must be valid when bit 17
(linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16,
Host
Controller Control Register
) is set to 1.
28
bmc
R/W
Bus manager capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in
the host controller control register at OHCI offset 50h/54h (see Section 4.16,
Host Controller Control
Register
) is set to 1.
27
pmc
R/W
Power-management capable. IEEE 1394 bus-management field. When bit 27 is set to 1, this indicates
that the node is power-management capable. Must be valid when bit 17 (linkEnable) in the host
controller control register at OHCI offset 50h/54h (see Section 4.16,
Host Controller Control Register
)
is set to 1.
2624
RSVD
R
Reserved. Bits 2624 return 0s when read.
2316
cyc_clk_acc
R/W
Cycle master clock accuracy, in parts per million. IEEE 1394 bus-management field. Must be valid
when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16,
Host Controller Control Register
) is set to 1.
1512
max_rec
R/W
Maximum request. IEEE 1394 bus-management field. Hardware initializes this field to indicate the
maximum number of bytes in a block request packet that is supported by the implementation. This
value, max_rec_bytes must be 512 or greater, and is calculated by 2^(max_rec + 1). Software may
change this field; however, this field must be valid at any time bit 17 (linkEnable) in the host controller
control register at OHCI offset 50h/54h (see Section 4.16,
Host Controller Control Register
) is set to
1. A received block write request packet with a length greater than max_rec_bytes may generate an
ack_type_error. This field is not affected by a software reset, and defaults to a value indicating
4096 bytes on a system (hardware) reset.
118
RSVD
R
Reserved. Bits 118 return 0s when read.
76
g
R/W
Generation counter. This field is incremented if any portion of the configuration ROM has been
incremented since the prior bus reset.
53
RSVD
R
Reserved. Bits 53 return 0s when read.
20
Lnk_spd
R
Link speed. This field returns 010, indicating that the link speeds of 100M bits/s, 200M bits/s, and
400M bits/s are supported.
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