參數(shù)資料
型號(hào)： TSB82AA2I
廠商： Texas Instruments, Inc.
英文描述： 1394b OHCI-LYNX CONTROLLER
中文描述： 的1394b OHCI的山貓控制器
文件頁(yè)數(shù)： 33/104頁(yè)
文件大?。?/td> 461K
代理商： TSB82AA2I
313
3.15 Interrupt Line and Pin Register
The interrupt line and pin register communicates interrupt line routing information. See Table 313 for a complete
description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Interrupt line and pin
Type
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
Interrupt line and pin
Read/Write, Read-only
3Ch
0100h
Table 313. Interrupt Line and Pin Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
158
INTR_PIN
R
Interrupt pin. Returns 01h when read, indicating that the TSB82AA2 PCI function signals interrupts on
the PCI_INTA terminal.
70
INTR_LINE
R/W
Interrupt line. This field is programmed by the system and indicates to software which interrupt line the
TSB82AA2 PCI_INTA is connected to.
3.16 MIN_GNT and MAX_LAT Register
The MIN_GNT and MAX_LAT register communicates to the system the desired setting of bits 158 in the latency timer
and class cache line size register at offset 0Ch in the PCI configuration space (see Section 3.7,
Latency Timer and
Class Cache Line Size Register
). If a serial EEPROM is detected, then the contents of this register are loaded through
the serial EEPROM interface after a PCI_RST. If no serial EEPROM is detected, then this register returns a default
value that corresponds to the MIN_GNT = 2, MAX_LAT = 4. See Table 314 for a complete description of the register
contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
MIN_GNT and MAX_LAT
Type
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
Default
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
Register:
Type:
Offset:
Default:
MIN_GNT and MAX_LAT
Read/Update
3Eh
0402h
Table 314. MIN_GNT and MAX_LAT Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
158
MAX_LAT
RU
Maximum latency. The contents of this field may be used by host BIOS to assign an arbitration priority level
to the TSB82AA2 device. The default for this field indicates that the TSB82AA2 device may need to access
the PCI bus as often as every 0.25
μ
s; thus, an extremely high priority level is requested. The contents of
this field may also be loaded through the serial EEPROM.
70
MIN_GNT
RU
Minimum grant. The contents of this field may be used by host BIOS to assign a latency timer register value
to the TSB82AA2 device. The default for this field indicates that the TSB82AA2 device may need to sustain
burst transfers for nearly 64
μ
s and thus request a large value be programmed in bits 158 of the TSB82AA2
latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see
Section 3.7,
Latency Timer and Class Cache Line Size Register
).
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