參數(shù)資料
型號(hào)： TSB82AA2I
廠商： Texas Instruments, Inc.
英文描述： 1394b OHCI-LYNX CONTROLLER
中文描述： 的1394b OHCI的山貓控制器
文件頁(yè)數(shù)： 35/104頁(yè)
文件大?。?/td> 461K
代理商： TSB82AA2I
315
3.19 Power Management Capabilities Register
The power management capabilities register indicates the capabilities of the TSB82AA2 device related to PCI power
management. See Table 317 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Power management capabilities
Type
RU
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
Register:
Type:
Offset:
Default:
Power management capabilities
Read/Update, Read-only
46h
7E02h
Table 317. Power Management Capabilities Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15
PME_D3COLD
RU
PCI_PME support from D3cold. This bit can be set to 1 or cleared to 0 via bit 15 (PME_D3COLD) in
the miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.23,
Miscellaneous Configuration Register
). The miscellaneous configuration register is loaded from ROM.
When this bit is set to 1, it indicates that the TSB82AA2 device is capable of generating a PCI_PME
wake event from D3cold. This bit state is dependent upon the TSB82AA2 VAUX implementation and
may be configured by using bit 15 (PME_D3COLD) in the miscellaneous configuration register (see
Section 3.23).
1411
PME_SUPPORT
R
PCI_PME support. This 4-bit field indicates the power states from which the TSB82AA2 device may
assert PCI_PME. This field returns a value of 1111b, indicating that PCI_PME may be asserted from
the D3hot, D2, D1, and D0 power states.
Bit 14 contains the value 1 to indicate that the PCI_PME signal can be asserted from the D3hot
state.
Bit 13 contains the value 1 to indicate that the PCI_PME signal can be asserted from the D2 state.
Bit 12 contains the value 1 to indicate that the PCI_PME signal can be asserted from the D1 state.
Bit 11 contains the value 1 to indicate that the PCI_PME signal can be asserted from the D0 state.
10
D2_SUPPORT
R
D2 support. Bit 10 is hardwired to 1, indicating that the function supports the D2 device power state.
9
D1_SUPPORT
R
D1 support. Bit 9 is hardwired to 1, indicating that the TSB82AA2 device supports the D1 power state.
86
AUX_CURRENT
R
Auxiliary current. This 3-bit field reports the 3.3-VAUX auxiliary current requirements. When bit 15
(PME_D3COLD) is cleared, this field returns 000b; otherwise, it returns 001b.
000b = Self-powered
001b = 55 mA (3.3-VAUX maximum current required)
Device-specific initialization. Bit 5 returns 0 when read, indicating that the TSB82AA2 device does not
require special initialization beyond the standard PCI configuration header before a generic class
driver is able to use it.
5
DSI
R
4
RSVD
R
Reserved. Bit 4 returns 0 when read.
3
PME_CLK
R
PME clock. Bit 3 returns 0 when read, indicating that no host bus clock is required for the TSB82AA2
device to generate PCI_PME.
20
PM_VERSION
R
Power-management version. This field returns 010b when read, indicating that the TSB82AA2 device
is compatible with the registers described in the
PCI Bus Power Management Interface Specification
(Revision 1.1).
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