參數(shù)資料
型號： TSB82AA2I
廠商： Texas Instruments, Inc.
英文描述： 1394b OHCI-LYNX CONTROLLER
中文描述： 的1394b OHCI的山貓控制器
文件頁數(shù)： 48/104頁
文件大?。?/td> 461K
代理商： TSB82AA2I
46
4.3
Asynchronous Transmit Retries Register
The asynchronous transmit retries register indicates the number of times the TSB82AA2 device attempts a retry for
asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 44 for
a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Asynchronous transmit retries
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Asynchronous transmit retries
Type
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
Asynchronous transmit retries
Read/Write, Read-only
08h
0000 0000h
Table 44. Asynchronous Transmit Retries Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
3129
secondLimit
R
The second limit field returns 0s when read, because outbound dual-phase retry is not
implemented.
2816
cycleLimit
R
The cycle limit field returns 0s when read, because outbound dual-phase retry is not implemented.
1512
RSVD
R
Reserved. Bits 1512 return 0s when read.
118
maxPhysRespRetries
R/W
This field tells the physical response unit how many times to attempt to retry the transmit operation
for the response packet when a busy acknowledge or ack_data_error is received from the target
node.
74
maxATRespRetries
R/W
This field tells the asynchronous transmit response unit how many times to attempt to retry the
transmit operation for the response packet when a busy acknowledge or ack_data_error is
received from the target node.
30
maxATReqRetries
R/W
This field tells the asynchronous transmit DMA request unit how many times to attempt to retry the
transmit operation for the response packet when a busy acknowledge or ack_data_error is
received from the target node.
4.4
CSR Data Register
The CSR data register accesses the bus management CSR registers from the host through compare-swap
operations. This register contains the data to be stored in a CSR if the compare is successful.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
CSR data
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
CSR data
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Register:
Type:
Offset:
Default:
CSR data
Read-only
0Ch
XXXX XXXXh
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