參數(shù)資料
型號(hào)： TSB82AA2I
廠商： Texas Instruments, Inc.
英文描述： 1394b OHCI-LYNX CONTROLLER
中文描述： 的1394b OHCI的山貓控制器
文件頁(yè)數(shù)： 36/104頁(yè)
文件大?。?/td> 461K
代理商： TSB82AA2I
316
3.20 Power Management Control and Status Register
The power management control and status register implements the control and status of the PCI power management
function. This register is not affected by the internally generated reset caused by the transition from the D3
hot
to D0
state. See Table 318 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Power management control and status
Type
RC
R
R
R
R
R
R
R/W
R
R
R
R
R
R
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
Power management control and status
Read/Clear, Read/Write, Read-only
48h
0000h
Table 318. Power Management Control and Status Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15
PME_STS
RC
Bit 15 is set to 1 when the TSB82AA2 device normally asserts the PME signal, independent of the state
of bit 8 (PME_ENB). This bit is cleared by a writeback of 1, which also clears the PCI_PME signal
driven by the TSB82AA2 device. Writing a 0 to this bit has no effect.
149
RSVD
R
Reserved. Bits 149 return 0s when read.
8
PME_ENB
R/W
When bit 8 is set to 1, PME assertion is enabled. When bit 8 is cleared, PME assertion is disabled. This
bit defaults to 0 if the function does not support PME generation from D3cold. If the function supports
PME from D3cold, then this bit is sticky and must be explicitly cleared by the operating system each time
it is initially loaded. Functions that do not support PME generation from any D-state (that is, bits 1511
in the power management capabilities register at offset 46h in the PCI configuration space (see
Section 3.19,
Power Management Capabilities Register
) equal 00000b), may hardwire this bit to be
read-only, always returning a 0 when read by system software.
72
RSVD
R
Reserved. Bits 72 return 0s when read.
10
PWR_STATE
R/W
Power state. This 2-bit field is used to set the TSB82AA2 device power state and is encoded as follows:
00 = Current power state is D0.
01 = Current power state is D1.
10 = Current power state is D2.
11 = Current power state is D3.
3.21 Power Management Extension Register
The power management extension register provides extended power-management features not applicable to the
TSB82AA2 device; thus, it is read-only and returns 0s when read. See Table 319 for a complete description of the
register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Power management extension
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
Power management extension
Read-only
4Ah
0000h
Table 319. Power Management Extension Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
150
RSVD
R
Reserved. Bits 150 return 0s when read.
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