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參數(shù)資料
| 型號： | TSB82AA2I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1394b OHCI-LYNX CONTROLLER |
| 中文描述： | 的1394b OHCI的山貓控制器 |
| 文件頁數(shù)： | 39/104頁 |
| 文件大?。?/td> | 461K |
| 代理商： | TSB82AA2I |
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319
Table 321. Miscellaneous Configuration Register (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
2
DISABLE_SCLKGATE
R/W
When bit 2 is set to 1, the internal SCLK runs identically with the chip input. This is a test
feature only and must be cleared to 0 (all applications).
1
DISABLE_PCIGATE
R/W
When bit 1 is set to 1, the internal PCI clock runs identically with the chip input. This is a test
feature only and must be cleared to 0 (all applications).
0
KEEP_PCLK
R/W
When bit 0 is set to 1, the PCI clock always is kept running through the PCI_CLKRUN
protocol. When this bit is cleared, the PCI clock can be stopped using PCI_CLKRUN.
3.24 Link Enhancement Control Register
The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial
EEPROM, if present. After these bits are set to 1, their functionality is enabled only if bit 22 (aPhyEnhanceEnable)
in the host controller control register at OHCI offset 50h/54h (see Section 4.16,
Host Controller Control Register
) is
set to 1. See Table 322 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Link enhancement control
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Link enhancement control
Type
R/W
R
R/W
R/W
R
R
R/W
R/W
R/W
R
R
R
R
R/W
R/W
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
Link enhancement control
Read/Write, Read-only
F4h
0000 0000h
Table 322. Link Enhancement Control Register Description
BIT
3116
15
14
FIELD NAME
RSVD
DisableATPipelining
EnableDraft
TYPE
R
R/W
R/W
DESCRIPTION
Reserved. Bits 3116 return 0s when read.
Disable AT pipelining. When bit 15 is set to 1, out-of-order AT pipelining is disabled.
Enable OHCI 1.2 draft features. When bit 14 is set to 1, it enables some features beyond the OHCI
1.1 specification. Specifically, this enables HCControl.LPS to be cleared by writing a 1 to the
HCControlClear.LPS bit and enables the link to set bit 9 in the xferStatus field of AR and IR
ContextControl registers.
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參數(shù)描述 |
|---|---|
| TSB82AA2IPGE | 功能描述:接口 - 專用 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| TSB82AA2IPGEEP | 功能描述:1394 接口集成電路 Mil Enh 1394b OHCI- Lynx Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB82AA2PGE | 功能描述:1394 接口集成電路 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB82AA2PGEG4 | 功能描述:1394 接口集成電路 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB82AA2ZGW | 功能描述:1394 接口集成電路 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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