參數(shù)資料
型號： TSB82AA2I
廠商： Texas Instruments, Inc.
英文描述： 1394b OHCI-LYNX CONTROLLER
中文描述： 的1394b OHCI的山貓控制器
文件頁數(shù)： 18/104頁
文件大?。?/td> 461K
代理商： TSB82AA2I
26
Table 25. 32-Bit PCI Bus Terminals (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
PCI_PAR
49
I/O
PCI parity. In all PCI bus read and write cycles, the TSB82AA2 device calculates even parity across the
PCI_AD31PCI_AD0 and PCI_C/BE0PCI_C/BE3 buses. As an initiator during PCI cycles, the TSB82AA2
device outputs this parity indicator with a one-PCI_CLK delay. As a target during PCI cycles, the calculated
parity is compared to the initiator parity indicator; a miscompare can result in a parity error assertion
(PCI_PERR).
PCI_PERR
47
I/O
PCI parity error indicator. This signal is driven by a PCI device to indicate that calculated parity does not match
PCI_PAR and/or PCI_PAR64 when PERR_ENB (bit 6) is set to 1 in the command register at offset 04h in the
PCI configuration space (see Section 3.4,
Command Register
).
PCI_PME
14
O
This terminal indicates wake events to the host. It is an open-drain signal which is asserted when PME_STS
is asserted and bit 8 (PME_ENB) in the PCI power management control and status register at offset 48h in the
PCI configuration space (see Section 3.20,
Power Management Control and Status Register
) has been set.
Bit 15 (PME_STS) in the PCI power management control and status register is set due to any unmasked
interrupt in the D0 (active) or D1 power state, and on a PHY_LINKON indication in the D2, D3, or D0
(uninitialized) power state.
PCI_REQ
13
O
PCI bus request. Asserted by the TSB82AA2 device to request access to the bus as an initiator. The host arbiter
asserts PCI_GNT when the TSB82AA2 device has been granted access to the bus.
PCI_SERR
48
O
PCI system error. When SERR_ENB (bit 8) in the command register at offset 04h in the PCI configuration space
(see Section 3.4,
Command Register
) is set to 1, the output is pulsed, indicating an address parity error has
occurred. The TSB82AA2 device need not be the target of the PCI cycle to assert this signal. This terminal is
implemented as open-drain.
PCI_STOP
46
I/O
PCI cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current PCI bus
transaction. This signal is used for target disconnects, and is commonly asserted by target devices which do
not support burst data transfers.
PCI_TRDY
44
I/O
PCI target ready. PCI_TRDY indicates the ability of the PCI bus target to complete the current data phase of
the transaction. A data phase is completed upon a rising edge of PCI_CLK where both PCI_IRDY and
PCI_TRDY are asserted.
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