參數(shù)資料
型號(hào): TSB82AA2I
廠商: Texas Instruments, Inc.
英文描述: 1394b OHCI-LYNX CONTROLLER
中文描述: 的1394b OHCI的山貓控制器
文件頁(yè)數(shù): 72/104頁(yè)
文件大?。?/td> 461K
代理商: TSB82AA2I
430
4.32 Node Identification Register
The node identification register contains the address of the node on which the OHCI-Lynx chip resides, and
indicates the valid node number status. The 16-bit combination of the busNumber field (bits 156) and the
NodeNumber field (bits 50) is referred to as the node ID. See Table 425 for a complete description of the register
contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Node identification
Type
RU
RU
R
R
RU
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Node identification
Type
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RU
RU
RU
RU
RU
RU
Default
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
Register:
Type:
Offset:
Default:
Node identification
Read/Write/Update, Read/Update, Read-only
E8h
0000 FFXXh
Table 425. Node Identification Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
iDValid
RU
Bit 31 indicates whether or not the TSB82AA2 device has a valid node number. It is cleared when a
1394 bus reset is detected, and set to 1 when the TSB82AA2 device receives a new node number from
its PHY device.
30
root
RU
Bit 30 is set to 1 during the bus reset process if the attached PHY device is root.
2928
RSVD
R
Reserved. Bits 2928 return 0s when read.
27
CPS
RU
Bit 27 is set to 1 if the PHY device is reporting that cable power status is OK.
2616
RSVD
R
Reserved. Bits 2616 return 0s when read.
156
BusNumber
RWU
This field identifies the specific 1394 bus the TSB82AA2 device belongs to when multiple
1394-compatible buses are connected via a bridge.
50
NodeNumber
RU
This field is the physical node number established by the PHY device during self-identification. It is
automatically set to the value received from the PHY device after the self-identification phase. If the
PHY device sets the NodeNumber to 63, then software must not set bit 15 (run) in the asynchronous
context control register (see Section 4.40,
Asynchronous Context Control Register
) for either of the
AT DMA contexts.
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