參數(shù)資料
型號(hào)： TSB82AA2I
廠商： Texas Instruments, Inc.
英文描述： 1394b OHCI-LYNX CONTROLLER
中文描述： 的1394b OHCI的山貓控制器
文件頁(yè)數(shù)： 87/104頁(yè)
文件大?。?/td> 461K
代理商： TSB82AA2I
445
4.46 Isochronous Receive Context Match Register
The isochronous receive context match register starts an isochronous receive context running on a specified cycle
number, filters incoming isochronous packets based on tag values, and waits for packets with a specified sync value.
The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See Table 436 for a
complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Isochronous receive context match
Type
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
0
0
0
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Isochronous receive context match
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
Register:
Type:
Offset:
Default:
Isochronous receive context match
Read/Write, Read-only
410Ch + (32 * n)
XXXX XXXXh
Table 436. Isochronous Receive Context Match Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
tag3
R/W
If bit 31 is set to 1, this context matches on isochronous receive packets with a tag field of 11b.
30
tag2
R/W
If bit 30 is set to 1, this context matches on isochronous receive packets with a tag field of 10b.
29
tag1
R/W
If bit 29 is set to 1, this context matches on isochronous receive packets with a tag field of 01b.
28
tag0
R/W
If bit 28 is set to 1, this context matches on isochronous receive packets with a tag field of 00b.
27
RSVD
R
Reserved. Bit 27 returns 0 when read.
2612
cycleMatch
R/W
Contains a 15-bit value, corresponding to the low-order two bits of cycleSeconds and the 13-bit
cycleCount field in the cycleStart packet. If bit 29 (cycleMatchEnable) in the isochronous receive
context control register (see Section 4.44,
Isochronous Receive Context Control Register
) is set to 1,
then this context is enabled for receives when the two low-order bits of the bus isochronous cycle timer
register at OHCI offset F0h (see Section 4.34,
Isochronous Cycle Timer Register
) cycleSeconds field
(bits 3125) and cycleCount field (bits 2412) value equal this field (cycleMatch) value.
118
sync
R/W
This 4-bit field is compared to the sync field of each isochronous packet for this channel when the
command descriptor w field is set to 11b.
7
RSVD
R
Reserved. Bit 7 returns 0 when read.
6
tag1SyncFilter
R/W
If bit 6 and bit 29 (tag1) are set to 1, then packets with tag 01b are accepted into the context if the two
most significant bits of the packet sync field are 00b. Packets with tag values other than 01b are filtered
according to bit 28 (tag0), bit 30 (tag2), and bit 31 (tag3) without any additional restrictions.
If this bit is cleared, then this context matches on isochronous receive packets as specified in
bits 2831 (tag0tag3) with no additional restrictions.
50
channelNumber
R/W
This 6-bit field indicates the isochronous channel number for which this isochronous receive DMA
context accepts packets.
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