參數(shù)資料
型號: TMP90C051
廠商: Toshiba Corporation
元件分類: 通用總線功能
英文描述: High Speed CMOS 8-bit Microcontroller,Integrating DMA, DRAM Controller,Serial Interface, Timer/Event Counter(高速 CMOS 8位微控制器(芯片集成了DMA,DRAM控制器,串行接口,定時器/事件計數(shù)器))
中文描述: 高速CMOS 8位微控制器,集成的DMA,DRAM控制器,串行接口,定時器/事件計數(shù)器(高速的CMOS 8位微控制器(DMA的芯片集成了,內(nèi)存控制器,串行接口,定時器/事件計數(shù)器))
文件頁數(shù): 81/158頁
文件大?。?/td> 4573K
代理商: TMP90C051
TOSHIBA CORPORATION
81/184
TMP90C051
Up-counter
This is an 8-bit binary counter that counts up in accordance
with the input clock specified with the timer 0 and 1
mode register (T01MOD) and timer 2 and 3 mode register
(T23MOD).
The timer 0/timer 2 input clock can be selected from
external clocks (TI0 and TI2) and the three internal
clocks T1, T4 and T16 by setting the T01MOD/
T23MOD registers.
The timer 1/timer 3 input clock differs depending on
the operating mode. In the 16-bit timer mode, the
timer 0/timer 2 output overflow is used as the input
clock.
In other than the 16-bit timer mode, the input clock is
selected from the internal clocks T1, T16 and
T256 by setting the T01MOD/T23MOD registers, and
the timer 0/timer 1 comparator output (match detec-
tion).
Examples: If T01MOD <T10M1, 0> = 01, the timer 0
overflow output is used as the timer 1
input clock (16-bit timer).
If T01MOD <T10M1, 0> = 00, and
T01MOD <T1CLK1, 0> = 01, T1 (8/fc) is
used as the timer 1 input clock (8-bit
timer).
The operating mode is also set using the T01MOD/
T23MOD registers. <T10M1, 0> and T23M1, 0> are
initialized to “00” by resets. This sets the 8-bit timer
mode.
Concerning the up counters, each interval timer can
be enabled, disabled or cleared with timer operation con-
trol register TRUN. All counters are cleared and timers
are stopped by resets.
Timer register
These are 8-bit registers used to set interval times.
When the values to which the timer registers (TREG0/
TREG1 and TREG2/TREG3) are set and the up
counter value match, the comparator match detect
signal becomes active. When the setting value is 00H,
the match detect signal becomes active in case of an
up counter overflow.
Timer registers TREG0/TREG2 have a double-buffer
configuration and these registers and buffers are used
as pairs.
The TREG0/TREG2 double buffer is enabled and disabled
with <TR0DE> and <TR2DE> of the timer register
double buffer control register (TRDC). The double
buffer is disabled when <TR0DE>/<TR2DE> = “0” and
enabled when <TR0DE>/<TR2DE> = “1”.
The timing for data transfers from a register buffer to a
timer register when double buffer has been enabled is
determined by compare matching of PWM mode 2
overflow or PPG mode cycle.
<TR0DE>/<TR2DE> are initialized to “0” by resets,
which disable double buffers. When using a double
buffer, write data to the timer register, set <TR0DE>/
<TR2DE> to “1” and then write the following data to
the register buffer.
n
- 1
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