參數(shù)資料
型號: TMP90C051
廠商: Toshiba Corporation
元件分類: 通用總線功能
英文描述: High Speed CMOS 8-bit Microcontroller,Integrating DMA, DRAM Controller,Serial Interface, Timer/Event Counter(高速 CMOS 8位微控制器(芯片集成了DMA,DRAM控制器,串行接口,定時器/事件計數(shù)器))
中文描述: 高速CMOS 8位微控制器,集成的DMA,DRAM控制器,串行接口,定時器/事件計數(shù)器(高速的CMOS 8位微控制器(DMA的芯片集成了,內存控制器,串行接口,定時器/事件計數(shù)器))
文件頁數(shù): 48/158頁
文件大小: 4573K
代理商: TMP90C051
48/184
TOSHIBA CORPORATION
TMP90C051
3.5 Standby Functions
Executing the HALT instruction sets the TMP90C051 to the
RUN, IDLE1 or STOP mode, depending on the contents of the
halt mode setting register. The features are shown below.
(1)
Run:
Only the CPU halts, power consumption
remains the same.
(2)
IDLE: Only the internal oscillators operate, all others
internal circuitry halts. Power consumption is
1/10 or less of that during operation.
(3)
STOP: All internal circuitry halts, including the
oscillators. Power consumption is extremely
reduced.
The HALT mode setting WDMOD <HLTM1, 0> is
assigned to bits 2 and 3 memory address FFDDH in the built-in
input/output register area (all other bits are used to control other
block functions). The “00” RUN mode is set by resets.
The halt status is released by interrupt requests and
resets. If interrupts are enabled, the CPU receives non-maskable
and maskable interrupts and starts interrupt processing. If
maskable interrupts are disabled, the CPU restarts execution
from the instruction following the HALT instruction but the
interrupt request flag remains at “1”.
If the halt status is released by reset, however, use caution
since the status in effect before entering the halt status cannot
be maintained. In such cases, it is recommended that inter-
rupt requests be used for releasing.
Figure 3.5 (1). Halt Mode Setting Register
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