參數(shù)資料
型號： TMP90C051
廠商： Toshiba Corporation
元件分類： 通用總線功能
英文描述： High Speed CMOS 8-bit Microcontroller,Integrating DMA, DRAM Controller,Serial Interface, Timer/Event Counter(高速 CMOS 8位微控制器（芯片集成了DMA,DRAM控制器，串行接口，定時器/事件計數(shù)器）)
中文描述： 高速CMOS 8位微控制器，集成的DMA，DRAM控制器，串行接口，定時器/事件計數(shù)器（高速的CMOS 8位微控制器（DMA的芯片集成了，內(nèi)存控制器，串行接口，定時器/事件計數(shù)器））
文件頁數(shù)： 119/158頁
文件大?。?/td> 4573K
代理商： TMP90C051
TOSHIBA CORPORATION
119/184
TMP90C051
3.10.3 Operation
(1)
Clock Selector
In the internal clock mode, it is possible to output the
transmit clock from TPHCK0 and select a clock rate
of T0 (fc/4), T1 (fc/8), T4 (fc/32), T16 (fc/128) from
the internal 9 bit prescaler (Timer Common use) (@
x’tal 12.5MHz: max. 3.125MHz/bit transfer at the 1/4
rate).
In the external clock mode, the clock input from
TPHCK1 is used for transmit operations (max. 4.0MHz/
bit). If a user uses the internal clock mode, operate the
prescaler.
(2)
Byte Counter
Bits TPHMOD <TRM1, 0> (Mode = 0) of the control
register (#FFEAH) are used to specify the number of
bytes to be transferred. The byte counter is reset to “0”
after one line has been transmitted.
(3)
TPHLAT Output
TPHLAT is set to “Low” active when the byte counter
has counted the number of bytes in one line.
(4)
LATWAIT Input
Wait control by software or from the external pin
(LATWAIT) can be used to wait for the TPHLAT output.
Waits are applied by keeping LATWAIT at low active
from the TPHCK0 fall that transmits the last bit of the
last byte of the transmits data to the next TPHCK0
rise.
(5)
Interrupt Generation
INTTX0: Generate at the trigger of the buffer empty
after TPH I/F transfer the 1 byte data
INTLINE: Generate at the trigger of 1 line data end with
TPHLAT output
Interrupt generation is enabled and disabled by setting
the INTE 1/2 register at address #FFCD/FFCEH. Interrupt
generation is disabled after a reset.
Table 3.10 (1) shows the interrupt generation sources
for SIO channel 0. Set SIO channel 0 interrupts as
shown below in accordance with the mode setting
(operating mode).
a) TPH Serial Interface Mode
Set the mode bit of TPHMOD <SMODE> to “0”.
When controlling the writing of transmit data to the
TPH serial interface from external pin INT3, set the
TPHSCR <EXINT> to “1”. In this case, transmit inter-
rupts are generated in accordance with the AND logic
of the internal transmit shift register status and external
pin INT3 status.
When the TPHSCR <EXINT>is set to “0”, transmit interrupts
are generated in accordance with the internal transmit
register status only.
(b)
UART, I/O Interface Mode
Set the TPHMOD <SMODE>to “1” and the
TPHSCR <EXINT> to “0”. Figure 3.10 (1) shows the
SIO channel 0 interrupt generation circuit.
Table 3.10 (1) Serial Channel 0 Interrupt Generation
Sources
Serial channel 0
mode
UART, Input/Output
interface mode
TPH mode
Start
External
Internal
External
Internal
Interrupt source
INTTX
–
INTTX
INTTXINT3
INTTX
INTRX
–
INTRX
–
–
INTLINE
–
–
INTLINE
相關(guān)PDF資料
PDF描述
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TMP90C800 High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit CPU,RAM，ROM，General Serial Interface,Timer/Event Counter(高速、先進的 CMOS 8位微控制器（芯片集成了8位CPU,ROM，RAM，通用串行接口，定時器/事件計數(shù)器）)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMP90C051F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
TMP90C141 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
TMP90C141F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
TMP90C141N 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
TMP90C400 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
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