參數(shù)資料
型號： TMP90C051
廠商： Toshiba Corporation
元件分類： 通用總線功能
英文描述： High Speed CMOS 8-bit Microcontroller,Integrating DMA, DRAM Controller,Serial Interface, Timer/Event Counter(高速 CMOS 8位微控制器（芯片集成了DMA,DRAM控制器，串行接口，定時器/事件計數(shù)器）)
中文描述： 高速CMOS 8位微控制器，集成的DMA，DRAM控制器，串行接口，定時器/事件計數(shù)器（高速的CMOS 8位微控制器（DMA的芯片集成了，內(nèi)存控制器，串行接口，定時器/事件計數(shù)器））
文件頁數(shù)： 104/158頁
文件大小： 4573K
代理商： TMP90C051
104/184
TOSHIBA CORPORATION
TMP90C051
Table 3.9 (2) Baud Rate Selection (2) (Using Timer: Input CLK T1) Unit: Kbps
fc
12.288
MHz
12
MHz
9.8304
MHz
8
MHz
6.144
MHz
TREG2
1H
96
–
76.8
62.5
48
2H
48
–
38.4
31.25
24
3H
32
31.25
–
–
16
4H
24
–
19.2
–
12
5H
19.2
–
–
–
9.6
8H
12
–
9.6
–
6
AH
9.6
–
–
–
4.8
10H
6
–
4.8
–
3
14H
4.8
–
–
–
2.4
Baud rate calculation method (using timer 2)
Input CLK of timer 2
T1 = fc/8
T4 = fc/32
T16 = fc/128
Serial clock generation circuit
This circuit generates the basic transmit/receive clock.
1) Input/output interface mode
In the SCCR0 <IOC0> = “1” SCLK0 output mode, the
output from the baud rate generator as described
above is divided by 2 to make the basic clock.
In the SCCR0 <IOC0> = “1” SCLK0 input mode,
either the rise or fall edge, as set with the SCCR0
<SCLK0> register, is detected to make the basic
clock.
2) Asynchronous communication (UART) mode
Either the baud rate generator clock described above,
the internal clock 1 (312.5k-baud @ 10MHz), or the
match detect signal from timer 2 is selected, as determined
by the SCMOD <SC01, 00> register settings, to make
the basic clock (SIOCLK).
Receive counter
The receive counter is a 4-bit binary counter used in
the asynchronous communication (UART) mode and
is counted up by SIOCLK. 16 SIOCLK clocks are
used to receive 1 bit of data and the data are sampled
at the 7th, 8th and 9th clocks.
The receive data are identified by majority logic by
sampling 3 times. For example, if the data 1, 0, 1 are
sampled by the 7th, 8th and 9th clocks, the data is
identified as “1”. If the values 0, 0, 1 are sampled, the
data is identified as “0”.
Receive control block
1) Input/output interface mode
In the SCCR0 <IOC0> = “0” SCLK0 output mode, the
RxD0 pin is sampled at the rise of the shift clock output to
the SCLK0 pin.
In the SCCR0 <IOC0> = “1” SCLK0 input mode, the
RxD0 pin is sampled at the rise/fall of the SCLK0 input
in accordance with the setting of the SCCR0 <IOC0>
register.
2) Asynchronous communication (UART) mode
The receive control block has a start bit detection circuit
that used majority logic. If “0” is detected twice or
more by sampling three times, the start bit is judged to
be correct and receiving starts.
Receive data are identified by majority logic even while
receiving data.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMP90C051F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
TMP90C141 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
TMP90C141F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
TMP90C141N 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
TMP90C400 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
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