參數(shù)資料
型號: TMP90C051
廠商: Toshiba Corporation
元件分類: 通用總線功能
英文描述: High Speed CMOS 8-bit Microcontroller,Integrating DMA, DRAM Controller,Serial Interface, Timer/Event Counter(高速 CMOS 8位微控制器(芯片集成了DMA,DRAM控制器,串行接口,定時器/事件計(jì)數(shù)器))
中文描述: 高速CMOS 8位微控制器,集成的DMA,DRAM控制器,串行接口,定時器/事件計(jì)數(shù)器(高速的CMOS 8位微控制器(DMA的芯片集成了,內(nèi)存控制器,串行接口,定時器/事件計(jì)數(shù)器))
文件頁數(shù): 14/158頁
文件大?。?/td> 4573K
代理商: TMP90C051
14/184
TOSHIBA CORPORATION
TMP90C051
Note: * HDMA supports all maskable interrupts.
Table 3.3 (1) Interrupt Sources
Priority
sequence
Type
Interrupt
function
name
Interrupt
vector
value
General-
purpose
interrupt
processing
start address
Micro
DMA
support
Micro DMA
processing
parameter start
address
Interrupt sources
Comments
Internal
External
1
2
Non-
maskable
S W I
Instruction
NMI
08H
10H
0008H
0010H
O
NMI pin
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Maskable
(HDMA)
INT0
INT1
INT2
INTT0
INTT1
INTT2
INTT3
INTRX0
INTTX0
INTLINE
INTRX1
INTTX1
INTALARM
INT3
INT4
INT5
INT6
INT7
18H
20H
28H
30H
38H
40H
48H
50H
58H
60H
68H
70H
78H
80H
88H
90H
98H
A0H
0018H
0020H
0028H
0030H
0038H
0040H
0048H
0050H
0058H
0060H
0068H
0070H
0078H
0080H
0088H
0090H
0098H
00A0H
O
O
O
O
O
O
O
O
O
O
O
O
FF18H
FF20H
FF28H
FF30H
FF38H
FF40H
FF48H
FF50H
FF58H
FF60H
FF68H
FF70H
Timer 0
Timer 1
Timer 2
Timer 3
Serial receive end
Serial send end
TPH send
Serial receive end
Serial receive end
Alarm output
INT0 pin
INT1 pin
INT2 pin
INT3 pin
INT4 pin
INT5 pin
INT6 pin
INT7 pin
* 1
External 0
External 1
External 2
Timer
Timer
Timer
Timer
SIO
SIO
TPH
SIO
SIO
RTC
External 3
External 4
External 5
External 6
External 7
The “priority sequence” shown in Table 3.3 (1) indicates
the sequence in which interrupt sources are received by the
CPU when multiple interrupt requests are generated simulta-
neously.
For example, if interrupt requests with the priority
sequences 4 and 5 are generated simultaneously, the CPU will
receive the interrupt request with priority sequence 4 first.
When processing of the interrupt with priority sequence 4 is
ended with the RETI instruction, the CPU will then receive the
interrupt with priority sequence 5.
If the interrupt processing program for the priority
sequence 4 interrupt is interrupted by executing the EI instruction,
the CPU will receive the priority sequence 5 interrupt request.
When multiple interrupt requests are generated simultaneously, the
built-in interrupt controller only determines the priority
sequence of the interrupt sources received by the CPU. There
is no function to compare the priority sequence of the interrupt
currently being processed and the interrupt currently being
requested.
Another interrupt can be enabled while another interrupt is
being processed by resetting the interrupt enable/disable flag
IFF to enable.
3.3.2 Micro DMA Processing
Figure 3.3 (3) shows the micro DMA processing flow. The CPU
first loads the parameters (transfer source and destination
addresses, transfer mode) required for transferring data
between memories from the address modified by the interrupt
vector value and then transfers the data between memories in
accordance with those parameters. After that, the revised
parameters are saved to the original location. The transfer
count is then decremented and, if the value is not “0”, micro
DMA processing is ended. If the value is “0”, the general-purpose
interrupt processing described in the previous item is performed.
The transfer count is decremented by “-1” each time the
micro DMA starts up.
*1)
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