參數(shù)資料
型號: TMP90C051
廠商: Toshiba Corporation
元件分類: 通用總線功能
英文描述: High Speed CMOS 8-bit Microcontroller,Integrating DMA, DRAM Controller,Serial Interface, Timer/Event Counter(高速 CMOS 8位微控制器(芯片集成了DMA,DRAM控制器,串行接口,定時(shí)器/事件計(jì)數(shù)器))
中文描述: 高速CMOS 8位微控制器,集成的DMA,DRAM控制器,串行接口,定時(shí)器/事件計(jì)數(shù)器(高速的CMOS 8位微控制器(DMA的芯片集成了,內(nèi)存控制器,串行接口,定時(shí)器/事件計(jì)數(shù)器))
文件頁數(shù): 5/158頁
文件大小: 4573K
代理商: TMP90C051
TOSHIBA CORPORATION
5/184
TMP90C051
Table 2.2. Pin Names and Functions (2/3)
Pin Name
Number of pins
(pin no.)
Input/outpu t or tristate
Function
P34
(DACT1)
1
(68)
Output
Port 34: A 1-bit output port. Outputs “1” after reset.
DMA active 1: Outputs zeros (0) while data are being transferred via high-speed micro DMA
channel 1.
P35
(WDTOUT)
1
(69)
Output
Port 35: A 1-bit output port. Outputs “WDTOUT = 1” after reset.
Watchdog timer output: used as the WDTOUT output pin when watchdog timer mode
register, D1 = 1.
P36
(INT7)
1
(70)
Input/Output
Input
Port 36: A 1-bit output port. Functions as an input port after reset.
Interrupt request pin 7: The input pin for generating interrupt requests at rise edges.
P37
1
(71)
Input/output
Port 37: A 1-bit input/output port. Functions as an input port after reset.
P40 ~ P43
4
(7 ~ 10)
Input/output
Port 40 - 43: A 4-bit input/output port. Functions as an input port after reset.
Output
Stepping motor control port 0.
P50 ~ P53
(M10
~ M03)
4
(11 ~ 14)
Input/output
Port 50 - 53: A 4-bit input/output port. Functions as an input port after reset.
Output
Stepping motor control port 1
P60 ~ P63
(INT3
~ INT6)
4
(15 ~ 18)
Input/output
Port 60 ~ 63: A 4-bit input/output port. Functions as an input port after reset.
Input
Interrupt request pins 3-6: Input pins for generating interrupt requests at rise edges.
P64
(TI0)
1
(19)
Input/output
Port 64: A 1-bit input/output port. Functions as an input port after reset.
Input
Timer input 0: The timer 0 clock input pin.
P65
(TI2)
1
(20)
Input/output
Port 65: A 1-bit input/output port. Functions as an input port after reset
Input
Timer input 2: The timer 2 clock input pin.
P66
(TO0/TO1)
1
(22)
Input/output
Port 66: A 1-bit input/output port. Functions as an input port after reset.
Output
Timer output 0/1: The timer 0 or timer 1 output pin.
P67
(TO2/TO3)
1
(23)
Input/output
Port 67: A 1-bit input/output port. Functions as an input port after reset.
Output
Timer output 2/3: The timer 2 or timer 3 output pin.
LATWAIT
RxD0
1
(30)
Input
Set serial channel 0 to the TPH mode after reset. The wait control input pin used to cause
TPHLAT output to wait.
Used as the receive data input pin when serial channel 0 is set to the Normal mode.
TPHSD
(TxD0)
1
(31)
Output
Serial channel 0 enters the TPH mode and outputs “0” after a reset. The TPHSD pin is used
to output transmit data to TPH.
When set to the Normal mode, serial channel 0 functions as the transmit data output pin
TXD0 output immediately after mode is set.
TPHCKO
(SCLK0)
1
(32)
Output
After a reset, serial channel 0 enters the TPH mode and outputs “1”. The TPHCK0 pin is used
to output the transmit clock to TPH.
Input/output
When set to the Normal mode by the TPH control register, serial channel 0 operates in the
UART or I/O interface mode.
The control register of serial channel 0 determines whether the UART or I/O interface mode is
used.
In the I/O interface mode, either the external clock from SCLK0 or the transmit/receive clock
from the internal baud rate generator is output. Note: When operating with external clock
inout in the I/O interface mode SCLK0 is output after a reset; therefore, use an open drain
circuit to connect the external clock to the SCLK0 pin.
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