參數(shù)資料
型號： TMP90C051
廠商： Toshiba Corporation
元件分類： 通用總線功能
英文描述： High Speed CMOS 8-bit Microcontroller,Integrating DMA, DRAM Controller,Serial Interface, Timer/Event Counter(高速 CMOS 8位微控制器（芯片集成了DMA,DRAM控制器，串行接口，定時器/事件計數(shù)器）)
中文描述： 高速CMOS 8位微控制器，集成的DMA，DRAM控制器，串行接口，定時器/事件計數(shù)器（高速的CMOS 8位微控制器（DMA的芯片集成了，內(nèi)存控制器，串行接口，定時器/事件計數(shù)器））
文件頁數(shù)： 13/158頁
文件大?。?/td> 4573K
代理商： TMP90C051
TOSHIBA CORPORATION
13/184
TMP90C051
3.3.1 General-Purpose Interrupt Processing
Figure 3.3 (2) shows the general-purpose interrupt processing
flow.
The CPU first saves the contents of the program counter
PC and register AF (including the interrupt enable/disable flag
IFF immediately before an interrupt) to the stack and then
resets the interrupt enable/disable flag IFF to “0” (interrupt
disable). Finally, the interrupt vector contents [V] are transferred to
the program counter and a jump is made to the interrupt
processing program.
There is a 20-state overhead from the time when the interrupt is
received until the jump is made to the interrupt processing program.
Figure 3.3 (2). General-Purpose Interrupt Processing Flow
Interrupt processing program is ended with the RETI
instruction for both maskable and non-maskable interrupts.
Executing this instruction restores the program counter
PC and register AF contents from the stack. (Resets the interrupt
enable/disable flag immediately before an interrupt.)
When the CPU reads the interrupt vector, the interrupt
request source confirms that the interrupt has been received
and then clears the interrupt request. Non-maskable interrupts
cannot be disabled by program. Maskable interrupts, how-
ever, can be enabled and disabled by program. Bit 5 of CPU reg-
ister F is an interrupt enable/disable flipflop (IFF). Interrupts are
enabled by setting this bit to “1” with the EI (interrupt enable)
instruction and disabled by resetting this bit to “0” with the DI
(interrupt disable) instruction. IFF is reset to “0” by resetting
and when an interrupt is received (including non-maskable
interrupts).
The EI instruction is actually executed after the next
instruction is executed.
Table 3.3 (1) shows the interrupt sources.
相關(guān)PDF資料
PDF描述
TMP90C141 High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit A/D Converter,General Serial Interface,Multifunction Timer/Event Counter(高速、先進(jìn)的 CMOS 8位微控制器（芯片集成了8位A/D轉(zhuǎn)換器,通用串行接口，多功能定時器/事件計數(shù)器）)
TMP90C400 High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit CPU,RAM，ROM，General Serial Interface,Multifunction Timer/Event Counter(高速、先進(jìn)的 CMOS 8位微控制器（芯片集成了8位CPU,ROM，RAM，通用串行接口，多功能定時器/事件計數(shù)器）)
TMP90C401 High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit CPU,RAM，ROM，General Serial Interface,Multifunction Timer/Event Counter(高速、先進(jìn)的 CMOS 8位微控制器（芯片集成了8位CPU,ROM，RAM，通用串行接口，多功能定時器/事件計數(shù)器）)
TMP90C800 High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit CPU,RAM，ROM，General Serial Interface,Timer/Event Counter(高速、先進(jìn)的 CMOS 8位微控制器（芯片集成了8位CPU,ROM，RAM，通用串行接口，定時器/事件計數(shù)器）)
TMP90C801 High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit CPU,RAM，ROM，General Serial Interface,Timer/Event Counter(高速、先進(jìn)的 CMOS 8位微控制器（芯片集成了8位CPU,ROM，RAM，通用串行接口，定時器/事件計數(shù)器）)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMP90C051F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
TMP90C141 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
TMP90C141F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
TMP90C141N 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
TMP90C400 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
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