參數(shù)資料
型號(hào)： SII3124ACBHU
元件分類(lèi)： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA364
封裝： 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364
文件頁(yè)數(shù)： 69/88頁(yè)
文件大小： 592K
代理商： SII3124ACBHU
PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
71
Reserved
S
DB
Notify
Hshk
Error
Thr
esh
CRC
E
rror
Thre
s
h
8b/10
Error
Thr
esh
D
evEx
c
hg
Unre
c
F
IS
C
o
mwake
PhyRdyChg
PM
Change
Port
R
eady
Command
Error
Cmd
Completion
Reserved
S
DB
Notify
Hshk
Error
Thr
esh
CRC
E
rror
Thre
s
h
8b/10
Error
Thr
esh
D
evEx
c
hg
Unre
c
F
IS
C
o
mwake
PhyRdyChg
PM
Change
Port
R
eady
Command
Error
Cmd
Completion
This register is used to report the interrupt status. The status bits in the upper half of the register report the described
condition. The status bits in the lower half of the register are masked by the corresponding interrupt enable bits or by the
setting in the corresponding threshold registers. Writing a 1 to either interrupt status bit clears it.
Bit [31:28,15:12]
: Reserved (R). These bits are reserved.
Bit [27/11]
: SDB Notify (W1C). This bit indicates that a Set Device Bits FIS was received with the N-bit (bit 15
of first dword) set to one.
Bit [26/10]
: Handshake Error Threshold (W1C). This bit indicates that the Handshake error count is equal to or
greater than the Handshake error threshold. Bit 10 is masked if the Handshake Error Threshold register contains
a zero threshold setting. When a 1 is written to this bit, both the status bit and the Handshake Error Counter are
cleared.
Bit [25/9]
: CRC Error Threshold (W1C). This bit indicates that the CRC error count is equal to or greater than
the CRC error threshold. Bit 9 is masked if the CRC Error Threshold register contains a zero threshold setting.
When a 1 is written to this bit, both the status bit and the CRC Error Counter are cleared.
Bit [24/8]
: 8b/10b Decode Error Threshold (W1C). This bit indicates that the 8b/10b Decode error count is
equal to or greater than the 8b/10b Decode error threshold.
Bit 8 is masked if the 8b/10b Decode Error
Threshold register contains a zero threshold setting. When a 1 is written to this bit, both the status bit and the
8b/10b Decode Error Counter are cleared.
Bit [23/7]
: DevExchg (Device Exchanged) (W1C) – This bit is the X bit in the DIAG field of the SError register. It
may be cleared by writing a corresponding one bit to either register.
Bit [22/6]
: UnrecFIS (Unrecognized FIS Type) (W1C) – This bit is the F bit in the DIAG field of the SError
register. It may be cleared by writing a corresponding one bit to either register.
Bit [21/5]
: ComWake (W1C) – This bit is the W bit in the DIAG field of the SError register. It may be cleared by
writing a corresponding one bit to either register.
Bit [20/4]
: PhyRdyChg (W1C) – This bit is the N bit in the DIAG field of the SError register. It may be cleared by
writing a corresponding one bit to either register.
Bit [19/3]
: PM Change (W1C). This bit indicates that a change has occurred in the power management state.
Bit [18/2]
:
Port Ready (W1C).
This bit indicates that the port has become ready to accept and execute
commands. This status indicates that Port Ready (bit 31 in the Port Status register) has made a 0 to 1 transition.
Clearing this status does not change the Port Ready bit in the Port Status register and this status is not set
subsequently until the Port Ready bit changes state.
Bit [17/1]
: Command Error (W1C). This bit indicates that an error occurred during command execution. The
error type can be determined via the port error register.
Bit [16/0]
:
Command Completion (W1C).
This bit indicates that one or more commands have completed
execution.
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