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參數(shù)資料
| 型號： | SII3124ACBHU |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA364 |
| 封裝： | 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364 |
| 文件頁數(shù)： | 40/88頁 |
| 文件大?。?/td> | 592K |
| 代理商： | SII3124ACBHU |
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PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
45
By default, a successfully completed command will set the command complete bit in the port Interrupt Status register. If the
Command Complete interrupt is enabled, an interrupt will be asserted simultaneously. The host driver may optionally set
control_interrupt_mask in the PRB Control field to prevent the command complete bit from being set on a per-command basis.
This is useful when the host issues a series of commands and wants to be interrupted only after a selected command
completes.
The command complete bit and associated interrupt will be cleared when the Slot Status register is read, unless the host
driver has set Interrupt No Clear on Read (Port Control Set/Clear register, bit 3). If Interrupt No Clear on Read is set to one,
the host driver must write a one to the Command Complete bit in the Interrupt Status Clear register in order to clear the
command complete bit and associated interrupt.
5.4.9
The Attention Bit
Bit 31 of the Slot Status register is the Attention bit. When set to one, it indicates that an enabled interrupt source, other than
command completion, is asserted. It is possible that the Slot Status register can indicate an Attention condition while also
showing that commands have successfully completed in bits 0 through 30. The interrupt service routine should always post-
process any completed commands in addition to servicing a possible Attention condition. The Attention bit is set only for
interrupt conditions that have been enabled as described in the Interrupt Sources section. The Attention bit will remain set to
one in the Slot Status register until all enabled interrupt conditions have been cleared.
5.4.10 Interrupt Service Procedure
The SiI3124 is designed to efficiently service interrupt events with minimal host overhead. There are a number of methods
that the host may use to quickly determine the interrupt cause within any of the ports. The Global Interrupt Status Register
(Global offset 0x44) may be read to determine which ports are interrupting. Then, the Slot Status Register for the interrupting
ports may be read to determine the interrupt cause. Alternately, if the bridge configuration allows bursting of pre-fetched read
data, all port Slot Status Registers may be read in a single burst operation from the Global Register space starting at Global
offset 0x00. If Interrupt No Clear on Read (port Control Register, Bit 3) is zero, any command complete interrupt will be
cleared when the Slot Status registers are read. The host driver should then compare the outstanding command status in bits
0 through 30 to its internal copy of outstanding commands to determine which, if any, commands have successfully
completed. Once the successful command completions have been noted, the host should check the Attention bit (bit 31) to
determine if any other enabled interrupt events are pending on the port. If the Attention bit is one, the host should read the
port Interrupt Status Register (Port offset (port*0x2000)+0x1008) to ascertain the cause for the Attention condition. Once the
Attention condition has been resolved and cleared, normal processing may continue.
5.4.11 Interrupt No Clear on Read
By default, the Command Completion interrupt condition is cleared when the port Slot Status Register is read. In some cases,
such as debug environments, clearing of the Command Completion interrupt might not be the desired effect of reading the Slot
Status Register. In these cases, the host driver should set the Interrupt No Clear on Read bit (bit 3) in the port Control
Register. When this bit is set, the host must clear the Command Completion interrupt by one of the following methods:
1.
Write a one to the corresponding port interrupt status bit(s) in the Global Interrupt Status Register (Global offset
0x44). Or,
2.
Write a one to bit 0 or bit 16 of the port Interrupt Status Register (Port offset (port*0x2000)+ 0x1008).
Method 1 allows Command Complete interrupts for multiple ports to be cleared in a single write operation. Method 2 will clear
Command Complete only for the corresponding port.
5.4.12 Error Processing
When an error occurs during command processing, the SiI3124 records the error condition and halts execution until the host
driver is able to restore normal operation. The SiI3124 does not attempt to automatically recover from error conditions.
Rather, it provides the host with the necessary information to handle the error condition. Errors that occur during command
execution cause the Command Error bit to be set to one in the port Interrupt Status Register (Port offset (port*0x2000)+
0x1008) and an error code to be placed in the port Command Error Register (Port offset (port*0x2000)+ 0x1024). Please see
section (xxx- Port Command Error register) for a complete list of possible error codes. Execution is then halted. Port Ready
(Port Status Register, bit 31) will be cleared to zero. Only the port with the error condition is halted. All other ports will
continue to process normally. If the Command Error interrupt is enabled, an interrupt is asserted and the Attention bit is
asserted in the port Slot Status Register. The corresponding Slot Status bit for the command in error will NOT be cleared to
zero, since the command did not complete successfully. If only non-queued commands are outstanding, the slot number for
the command in error is available in the Port Status Register, bits[20:16]. The host may use this information to ascertain which
outstanding command caused the error condition.
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