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參數資料
| 型號： | SII3124ACBHU |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA364 |
| 封裝： | 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364 |
| 文件頁數： | 49/88頁 |
| 文件大小： | 592K |
| 代理商： | SII3124ACBHU |
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PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
53
7.1.4
BIST – Header Type – Latency Timer – Cache Line Size
Address Offset: 0CH
Access Type: Read/Write
Reset Value: 0x0000_0000 (PCI) / 0x0000_4000 (PCI-X)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
BIST
Header Type
Latency Timer
Cache Line Size
This register defines the various control functions associated with the PCI bus. The register bits are defined below.
Bit [31:24]
: BIST (R). This bit field is hardwired to 00H.
Bit [23:16]
: Header Type (R). This bit field is hardwired to 00H.
Bit [15:08]
: Latency Timer (R/W). This bit field is used to specify the time in number of PCI clocks, the SiI3124
as a master is still allowed to control the PCI bus after its GRANT_L is deasserted. The lower four bits [0B:08]
are hardwired to 0H, resulting in a time granularity of 16 clocks. The reset value is 00H for PCI; 40H for PCI-X.
Bit [07:00]
: Cache Line Size (R/W). This bit field is used to specify the system cacheline size in terms of 32-bit
words. The SiI3124, when initiating a read transaction, will issue the Read Multiple PCI command if empty
space in its FIFO is greater than the value programmed in this register.
7.1.5
Base Address Register 0
Address Offset: 10H
Access Type: Read/Write
Reset Value: 0x0000_0000_0000_0004
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Base Address Register 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Base Address Register 0
0000100
This register defines the addressing of the Global Registers within the SiI3124. The register bits are defined below.
Bit [63:07]
: Base Address Register 0 (R/W). This register defines the base address for the 128-byte Memory
Space containing the Global Registers.
Bit [06:00]
: (R). This bit field is hardwired to 0000100B to indicate a 64-bit base address.
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