參數(shù)資料
型號(hào): SII3124ACBHU
元件分類(lèi): 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA364
封裝: 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364
文件頁(yè)數(shù): 4/88頁(yè)
文件大?。?/td> 592K
代理商: SII3124ACBHU
PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
12
2.4 CLKI SerDes Reference Clock Input Requirements
Limits
Symbol
Parameter
Condition
Min
Typ
Max
Unit
TCLKI_FREQ
Nominal Frequency
REXT = 1k 1%
REXT = 4.99k 1%
25
100
MHz
VCLKI_IH
Input High Voltage
-
0.7xVDDRX
V
VCLKI_IL
Input Low Voltage
-
0.3xVDDRX
V
TCLKI_J
CLKI frequency tolerance
-
-50
+50
ppm
25MHz reference, 20%-80%
4
TCLKI_RISE_FALL Rise and Fall time at CLKI
100MHz reference, 20%-80%
2
ns
TCLKI_RJ
Random Jitter
Measured at CLKI pin
10
-12 Bit Error Ratio
1 sigma deviation
50
psrms
TCLKI_TJ
Total Jitter
Measured at CLKI pin
10
-12 Bit Error Ratio
peak-to-peak phase noise
1
ns
TCLKI_RC_DUTY CLKI duty cycle
20%-80%
40
60
%
Table 2-7 CLKI SerDes Reference Clock Input Requirements
2.5 Power Supply Noise Requirements
Limits
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VNOISE_VDDA 1.8V Analog Power Noise
50
mV
VNOISE_VDDD 1.8V Digital Power Noise
100
mV
VNOISE_VDDO 3.3V IO Power Noise
peak-to-peak sinewave across
500KHz to 3GHz frequency
range.
Measured with differential probe
trigger by nois source (CLKI and
PCI_CLK)
200
mV
Table 2-8 Power Supply Noise Requirements
2.6 PCI 33 MHz Timing Specifications
Limits
Symbol
Parameter
Min
Max
Unit
TVAL
CLK to Signal Valid – Bussed Signals
2.0
11.0
ns
TVAL (PTP)
CLK to Signal Valid – Point to Point
2.0
11.0
ns
TON
Float to Active Delay
2.0
-
ns
TOFF
Active to Float Delay
-
28.0
ns
TSU
Input Setup Time – Bussed Signals
7.0
-
ns
TSU (PTP)
Input Setup Time – Point to Point
10.0
-
ns
TH
Input Hold Time
0.0
-
ns
Table 2-9 PCI 33 MHz Timing Specifications
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