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參數(shù)資料
| 型號： | SII3124ACBHU |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA364 |
| 封裝： | 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364 |
| 文件頁數(shù)： | 35/88頁 |
| 文件大小： | 592K |
| 代理商： | SII3124ACBHU |
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PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
40
5.4.3
Port Ready
Each port contains a Port Ready indicator (Port Status, bit 31) that is cleared to zero by any of the above reset conditions.
The Port Ready signal, when one, indicates that the port is ready to execute commands. For all resets except Port Initialize,
the Port Ready signal will not be asserted until a PHY ready condition is achieved. When Port Initialize is set, Port Ready will
be cleared to zero then set to one after any currently active data transfers or FIS transmission/reception operations have
completed and port initialization has completed.
5.4.4
Port Reset Operation
Upon release of Port Reset, the low-level power management state machine is enabled and OOB signaling is initiated to the
device. The SiI3124 starts OOB signaling by transmitting a COMRESET to the device. If the device responds with COMINIT
and the OOB sequence is successful, a PHY ready condition will result, indicating that a link has been successfully
established and the device may transmit an initial register FIS. At this time, the Port Ready signal will be asserted, indicating
that the host driver may issue commands. If the device does not respond within the prescribed time allowed for OOB, the low-
level power management machine will initiate another OOB sequence after a fixed delay. The period between OOB attempts
is approximately 100 milliseconds.
Upon receipt of an initial “Register – Device to Host” FIS that clears the task file status BSY state, the port is allowed to
transmit commands to the device.
5.4.5
Initialization Sequence
The following is an example sequence of events that software might use to initialize the SiI3124 and enumerate an attached
device or port multiplier. The sequence assumes that the system has powered up, the PCI(X) Reset has been de-asserted,
and the system has enumerated the PCI(X) bus. Configuration space, including the Base Address Registers, has been
initialized. It is now necessary to enable each port and determine the device type, if any, that is attached to each port.
1.
Remove the Global Reset by writing 0x00000000 to the Global Control Register (Global offset 0x40).
2.
For each Port to be initialized:
a.
Clear Port Reset by writing one to Port Reset of Port Control Clear Register (Port offset
(port*0x2000)+0x1004, bit 0).
b.
If 32-bit platform and 32-bit activation is desired, write one to 32-bit Activation of Port Control Set Register
(Port offset (port*0x2000)+0x1000, bit 10).
c.
To enable interrupts for command completion and command errors, write 0x00000003 to the Port Interrupt
Enable Set Register (Port offset (port*0x2000)+0x1010).
d.
To determine if device is present, poll the SStatus Register (Port offset (port*0x2000)+0x1f04) for a
PHYRDY condition indicated by the DET field (bits[3:0]) having a value of 0x3.
e.
Wait until Port Ready in Port Status Register (Port offset (port*0x2000)+0x1000, bit 31) is one. If desired, an
interrupt may be armed in the Port Interrupt Set Register (bit 2). Any change in Port Ready state will assert
an interrupt.
f.
If the software supports port multipliers, build a Soft Reset PRB in host memory. Set the PMP field to 0x0f
to direct the command to the control port of a port multiplier. Issue the command to any available slot. If the
software does not support port multipliers, skip this step, as sending this command will cause the port
multiplier to disable legacy access to device 0.
g.
Upon successful command completion of the soft reset command, read the device signature from the
command slot (Port offset (port*0x2000)+(slot*0x80)+0x14(LSB), 0x0c, 0x0d, 0x0e(MSB)).
h.
If the signature is 0x96690101, then the attached device is a Port Multiplier. Perform the Port Multiplier
Enumeration procedure:
i.
Enable Port Multiplier context switching by writing a one to PM Enable in the Port Control Set
Register (Port offset (port*0x2000)+0x1000, bit 13).
ii.
Read the Port Multiplier GSCR[2] register by issuing a Read Port Multiplier command to the control
port. This register contains the number of device ports on the Port Multiplier.
iii.
For each Port Multiplier Device Port:
1.
Enable the PHY by writing a 1, then a 0 to the Scontrol Register (PSCR[2]) DET field.
Issue a Port Multiplier Write command for each of these operations.
2.
Wait for a PHYRDY condition in the port by polling the SStatus Register (PSCR[0]) .
3.
Clear the X-bit and all other error bits in the Serror Register (PSCR[1]) by writing all ones
to the register with a Write Port Multiplier command. The port is now ready for operation.
4.
Issue a Soft Reset command with the PMP field set to the appropriate port. This will
return a device signature for the attached device.
5.
Issue the appropriate Identify Device or Identify Packet Device command and any
associated Set Features, Set Write Multiple commands as may be necessary to initialize
the device.
i.
If the signature is 0xeb140101, then the attached device is an ATAPI PACKET device.
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