參數(shù)資料
型號： SII3124ACBHU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA364
封裝： 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364
文件頁數(shù)： 57/88頁
文件大?。?/td> 592K
代理商： SII3124ACBHU
PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
60
This register defines the power management capabilities associated with the PCI bus. The register bits are defined below.
Bit [31:24]
: PPM Data (R) – PCI Power Management Data. This bit field is hardwired to 0x19 to indicate a
power consumption of 2.5 Watt.
Bit [23:16]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [15]
: PME Status (R) – PME Status. This bit is hardwired to 0. The SiI3124 does not support PME.
Bit [14:13]
: PPM Data Scale (R) – PCI Power Management Data Scale. This bit field is hardwired to 01B to
indicate a scaling factor of 100 milliwatts.
Bit [12:09]
: PPM Data Sel (R/W) – PCI Power Management Data Select. This bit field is set by the system to
indicate which data field is to be reported through the PPM Data bits (although current implementation hardwires
the PPM Data to indicate 2.5 Watt).
Bit [08]
: PME Ena (R) – PME Enable. This bit is hardwired to 0. The SiI3124 does not support PME.
Bit [07:02]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [01:00]
: PPM Power State (R/W) – PCI Power Management Power State. This bit field is set by the system
to dictate the current Power State: 00 = D0 (Normal Operation), 01 = D1, 10 = D2, and 11 = D3 (Hot).
7.2 Internal Register Space – Base Address 0
These registers are 32 or 64 bits wide and are the Global Registers of the SiI3124. Access to this register space is through
the PCI Memory space. In the following table a dashed line separates the register pairs that may be accessed as a 64-bit
register.
Address Offset
Register Name
00H
Port 0 Slot Status
04H
Port 1 Slot Status
08H
Port 2 Slot Status
0CH
Port 3 Slot Status
10H-3FH
Reserved
40H
Global Control
44H
Global Interrupt Status
48H
PHY Configuration
4C H-6FH
Reserved
50H
BIST Control
54H
BIST Pattern
58H
BIST Status
70H
Flash Address
74H
GPIO
Flash Data
78H
I
2C Address
7CH
I
2C Control
Reserved
I
2C Data
Table 7-2 SiI3124 Internal Register Space – Base Address 0
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