- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98080 > SII3124ACBHU PCI BUS CONTROLLER, PBGA364 PDF資料下載
參數(shù)資料
| 型號： | SII3124ACBHU |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA364 |
| 封裝： | 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364 |
| 文件頁數(shù)： | 53/88頁 |
| 文件大?。?/td> | 592K |
| 代理商： | SII3124ACBHU |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁當前第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
57
7.1.12 PCI-X Capability
Address Offset: 40H
Access Type: Read/Write
Reset Value: 0x0052_5407
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Max Split
Ma
x
Me
m
Rd
En
Rlxd
Ord
P
E
RR
Rc
v
r
Next Capability Pointer
Capability ID
This register defines the PCI-X Capability. The register bits are defined below.
Bit [31:23]
: Reserved (R) – This bit field is reserved and returns zeros on a read.
Bit [22:20]
:
Max Split (R/W) – Maximum Outstanding Split Transactions.
This bit field sets the maximum
number of split transactions the device is permitted to have outstanding.
This field is initialized to 101B to
indicate a maximum of 12 outstanding split transactions possible.
Bit [19:18]
: Max Mem Rd (R/W) – Maximum Memory Read Byte Count. This bit field is initialized to 00B.
Bit [17]
: En Rlxd Ord (R/W) – Enable Relaxed Ordering. This bit field defaults to 1 to enable relaxed ordering of
memory transactions.
Bit [16]
: PERR Rcvr (R/W) – Data Parity Recovery Enable. The host driver may set this bit if it can attempt to
recover from data parity errors. If this bit is 0, a System Error will be generated if a data parity error is detected.
Bit [15:08]
: Next Capability Pointer (R) –Next Capability Pointer. This bit field is hardwired to 54H to point to the
3
rd Capabilities register, the MSI Capability.
Bit [07:00]
: Capability ID (R) – PCI Capability ID. This bit field is hardwired to 07H to indicate that this is a PCI-X
Capability.
7.1.13 PCI-X Status
Address Offset: 44H
Access Type: Read/Write/W1C
Reset Value: 0x12C3_FFF8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
R
eser
ved
Split
Comp
Err
Ma
x
Cum
Rd
M
ax
Split
Ma
x
Rd
BC
D
vc
C
m
plx
U
n
Exp
Split
Disc
ard
133
M
H
z
64-
bit
Bus Number
Device Number
Function
Number
This register defines the PCI-X capabilities and current operating status of the PCI-X bus. The register bits are defined below.
Bit [31:30]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [29]
:
Split Comp Err (R/W1C) – Received Split Completion Error Message.
This bit is set if a split
completion message is received with the split completion error attribute bit set.
Bit [28:26]
: Max Cum Rd (R) – Designed Maximum Cumulative Read Size. This bit field is hardwired to 100B;
this corresponds to a maximum 16K byte cumulative outstanding burst memory read transactions.
Bit [25:23]
: Max Split (R) – Designed Maximum Outstanding Split Transactions. This bit field is hardwired to
101B; this corresponds to a maximum of 12 outstanding split transactions.
Bit [22:21]
: Max Rd BC (R) – Designed Maximum Memory Read Byte Count. This bit field is hardwired to 10B;
this corresponds to a maximum of 2K bytes for a memory read transaction.
Bit [20]
: DVC Cmplx (R) – Device Complexity. This bit is hardwired to 0; the SiI3124 is not a bridge.
Bit [19]
: UnExp Split (W1C) – Unexpected Split Completion.
This bit indicates that an unexpected split
completion was received.
Bit [18]
: Split Discard (W1C) – Split Completion Discarded. This bit indicates that a split completion has been
discarded.
Bit [17]
: 133 MHz (R) – 133 MHz Capable. This bit is hardwired to 1.
Bit [16]
: 64-bit (R) – 64-bit Device. This bit is hardwired to 1.
Bit [15:8]
: Bus Number (R) – This bit field is initialized to FFH.
Bit [7:3]
: Device Number (R) – This bit field is initialized to 1FH.
Bit [2:0]
: Function Number (R) – This bit field is hardwired to 0H.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SII3512ECTU128 | PCI BUS CONTROLLER, PQFP128 |
| SII3531ACNU | PCI BUS CONTROLLER, QCC48 |
| SIO10N268-NU | MULTIFUNCTION PERIPHERAL, PQFP128 |
| SIS300 | GRAPHICS PROCESSOR, PBGA365 |
| SK12430PJT | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII3132 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI Express to 2-Port Serial ATA II Host Controller |
| SII3132CNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 88-Pin QFN |
| SII3512 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI to Serial ATA Controller |
| SII3512ECTU128 | 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 128-Pin TQFP 制造商:Silicone Image 功能描述: |
| SII3531 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:SteelVine⑩ Host Controller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。